/** ============================================================================
* @n@b Setup_Rx
*
* @b Description
* @n This API sets up all relevant data structures and configuration required
* for receiving data from PASS/Ethernet. It sets up a Rx free descriptor queue
* with some empty pre-allocated buffers to receive data, and an Rx queue
* to which the Rxed data is streamed for the example application. This API
* also sets up the QM high priority accumulation interrupts required to
* receive data from the Rx queue.
*
* @param[in]
* @n None
*
* @return Int32
* -1 - Error
* 0 - Success
* =============================================================================
*/
Int32 Setup_Rx (Ethernet *pThis)
{
Int32 result;
UInt8 isAllocated, accChannelNum;
UInt16 numAccEntries, intThreshold, i;
Qmss_Queue rxFreeQInfo, rxQInfo;
Ptr pCppiDesc;
Qmss_AccCmdCfg accCfg;
Cppi_RxFlowCfg rxFlowCfg;
Ptr pDataBuffer;
Error_Block eb;
Uint32 mySWInfo[] = {0x11112222, 0x33334444};
/* Open a Receive (Rx) queue.
*
* This queue will be used to hold all the packets received by PASS/CPSW
*
* Open the next available High Priority Accumulation queue for Rx.
*/
if ((gRxQHnd = Qmss_queueOpen (Qmss_QueueType_HIGH_PRIORITY_QUEUE, QMSS_PARAM_NOT_SPECIFIED, &isAllocated)) < 0)
{
uart_write ("Error opening a High Priority Accumulation Rx queue \n");
return -1;
}
rxQInfo = Qmss_getQueueNumber (gRxQHnd);
uart_write ("Opened RX queue Number %d \n",rxQInfo.qNum);
/* Setup high priority accumulation interrupts on the Rx queue.
*
* Let's configure the accumulator with the following settings:
* (1) Interrupt pacing disabled.
* (2) Interrupt on every received packet
*/
intThreshold = RX_INT_THRESHOLD;
numAccEntries = (intThreshold + 1) * 2;
accChannelNum = PA_ACC_CHANNEL_NUM;
/* Initialize the accumulator list memory */
memset ((Void *) gHiPriAccumList, 0, numAccEntries * 4);
/* Ensure that the accumulator channel we are programming is not
* in use currently.
*/
result = Qmss_disableAccumulator (Qmss_PdspId_PDSP1, accChannelNum);
if (result != QMSS_ACC_SOK && result != QMSS_ACC_CHANNEL_NOT_ACTIVE)
{
uart_write ("Error Disabling high priority accumulator for channel : %d error code: %d\n",
accChannelNum, result);
return -1;
}
/* Setup the accumulator settings */
accCfg.channel = accChannelNum;
accCfg.command = Qmss_AccCmd_ENABLE_CHANNEL;
accCfg.queueEnMask = 0;
accCfg.listAddress = Convert_CoreLocal2GlobalAddr((Uint32) gHiPriAccumList);
// accCfg.listAddress = gHiPriAccumList;
accCfg.queMgrIndex = gRxQHnd;
accCfg.maxPageEntries = (intThreshold + 1); /* Add an extra entry for holding the entry count */
accCfg.timerLoadCount = 0;
accCfg.interruptPacingMode = Qmss_AccPacingMode_LAST_INTERRUPT;
accCfg.listEntrySize = Qmss_AccEntrySize_REG_D;
accCfg.listCountMode = Qmss_AccCountMode_ENTRY_COUNT;
accCfg.multiQueueMode = Qmss_AccQueueMode_SINGLE_QUEUE;
/* Program the accumulator */
if ((result = Qmss_programAccumulator (Qmss_PdspId_PDSP1, &accCfg)) != QMSS_ACC_SOK)
{
uart_write ("Error Programming high priority accumulator for channel : %d queue : %d error code : %d\n",
accCfg.channel, accCfg.queMgrIndex, result);
return -1;
}
Error_init(&eb);
pThis->RxEventHandle = Event_create(NULL,&eb);
if (pThis->RxEventHandle == NULL)
{
uart_write("Event create failed");
return -1;
}
memset(pThis->pRxDataPtr,0,sizeof(pThis->pRxDataPtr));
pThis->RxDataHead = 0;
pThis->RxDataTail = 0;
Intr_Init(&pThis->oEthIntr, INTR_ITEM_ETH_RX,(Intr_Handler)Cpsw_RxISR, (void*)pThis);
/* Open a Rx Free Descriptor Queue (Rx FDQ).
*
* This queue will hold all the Rx free decriptors. These descriptors will be
* used by the PASS CPDMA to hold data received via CPSW.
*/
if ((gRxFreeQHnd = Qmss_queueOpen (Qmss_QueueType_STARVATION_COUNTER_QUEUE, QMSS_PARAM_NOT_SPECIFIED, &isAllocated)) < 0)
{
uart_write ("Error opening Rx Free descriptor queue \n");
return -1;
}
rxFreeQInfo = Qmss_getQueueNumber (gRxFreeQHnd);
uart_write("Opened RX Free queue Number %d\n",gRxFreeQHnd);
/* Attach some free descriptors to the Rx free queue we just opened. */
for (i = 0; i < NUM_RX_DESC; i++)
{
/* Get a free descriptor from the global free queue we setup
* during initialization.
*/
if ((pCppiDesc = Qmss_queuePop (gGlobalFreeQHnd)) == NULL)
{
break;
}
/* The descriptor address returned from the hardware has the
* descriptor size appended to the address in the last 4 bits.
*
* To get the true descriptor size, always mask off the last
* 4 bits of the address.
*/
pCppiDesc = (Ptr) ((UInt32) pCppiDesc & 0xFFFFFFF0);
if ((pDataBuffer = (Ptr) Memory_alloc((IHeap_Handle)heap2, ETHER_MAX_SIZE, 0, NULL)) == NULL)
{
uart_write ("Error allocating memory for Rx data buffer \n");
break;
}
/* Populate the Rx free descriptor with the buffer we just allocated. */
Cppi_setData (Cppi_DescType_HOST, pCppiDesc, (UInt8 *)Convert_CoreLocal2GlobalAddr((UInt32)pDataBuffer), ETHER_MAX_SIZE);
/* Save original buffer information */
Cppi_setOriginalBufInfo (Cppi_DescType_HOST, pCppiDesc, (UInt8 *)Convert_CoreLocal2GlobalAddr((UInt32)pDataBuffer), ETHER_MAX_SIZE);
/* Setup the Completion queue:
*
* Setup the return policy for this desc to return to the free q we just
* setup instead of the global free queue.
*/
Cppi_setReturnQueue (Cppi_DescType_HOST, pCppiDesc, rxFreeQInfo);
Cppi_setSoftwareInfo (Cppi_DescType_HOST, pCppiDesc, (UInt8 *) mySWInfo);
Cppi_setPacketLen (Cppi_DescType_HOST, pCppiDesc, ETHER_MAX_SIZE);
/* Push descriptor to Tx free queue */
Qmss_queuePushDescSize (gRxFreeQHnd, pCppiDesc, SIZE_CPSW_HOST_DESC);
}
if (i != NUM_RX_DESC)
{
uart_write ("Error allocating Rx free descriptors \n");
return -1;
}
//count=Qmss_getQueueEntryCount(gRxFreeQHnd);
//platform_write("Total %d entries in queue %d\n",count,gRxFreeQHnd);
/* Setup a Rx Flow.
*
* A Rx flow encapsulates all relevant data properties that CPDMA would
* have to know in order to succefully receive data.
*/
/* Initialize the flow configuration */
memset (&rxFlowCfg, 0, sizeof(Cppi_RxFlowCfg));
/* Let CPPI pick the next available flow */
rxFlowCfg.flowIdNum = CPPI_PARAM_NOT_SPECIFIED;
rxFlowCfg.rx_dest_qmgr = rxQInfo.qMgr;
rxFlowCfg.rx_dest_qnum = rxQInfo.qNum;
rxFlowCfg.rx_desc_type = Cppi_DescType_HOST;
rxFlowCfg.rx_ps_location = Cppi_PSLoc_PS_IN_DESC;
rxFlowCfg.rx_psinfo_present = 1; /* Enable PS info */
rxFlowCfg.rx_error_handling = 0; /* Drop the packet, do not retry on starvation by default */
rxFlowCfg.rx_einfo_present = 1; /* EPIB info present */
rxFlowCfg.rx_dest_tag_lo_sel = 0; /* Disable tagging */
rxFlowCfg.rx_dest_tag_hi_sel = 0;
rxFlowCfg.rx_src_tag_lo_sel = 0;
rxFlowCfg.rx_src_tag_hi_sel = 0;
rxFlowCfg.rx_size_thresh0_en = 0; /* By default, we disable Rx Thresholds */
rxFlowCfg.rx_size_thresh1_en = 0; /* By default, we disable Rx Thresholds */
rxFlowCfg.rx_size_thresh2_en = 0; /* By default, we disable Rx Thresholds */
rxFlowCfg.rx_size_thresh0 = 0x0;
rxFlowCfg.rx_size_thresh1 = 0x0;
rxFlowCfg.rx_size_thresh2 = 0x0;
rxFlowCfg.rx_fdq0_sz0_qmgr = rxFreeQInfo.qMgr; /* Setup the Receive free queue for the flow */
rxFlowCfg.rx_fdq0_sz0_qnum = rxFreeQInfo.qNum;
rxFlowCfg.rx_fdq0_sz1_qnum = 0x0;
rxFlowCfg.rx_fdq0_sz1_qmgr = 0x0;
rxFlowCfg.rx_fdq0_sz2_qnum = 0x0;
rxFlowCfg.rx_fdq0_sz2_qmgr = 0x0;
rxFlowCfg.rx_fdq0_sz3_qnum = 0x0;
rxFlowCfg.rx_fdq0_sz3_qmgr = 0x0;
rxFlowCfg.rx_fdq1_qnum = rxFreeQInfo.qNum; /* Use the Rx Queue to pick descriptors */
rxFlowCfg.rx_fdq1_qmgr = rxFreeQInfo.qMgr;
rxFlowCfg.rx_fdq2_qnum = rxFreeQInfo.qNum; /* Use the Rx Queue to pick descriptors */
rxFlowCfg.rx_fdq2_qmgr = rxFreeQInfo.qMgr;
rxFlowCfg.rx_fdq3_qnum = rxFreeQInfo.qNum; /* Use the Rx Queue to pick descriptors */
rxFlowCfg.rx_fdq3_qmgr = rxFreeQInfo.qMgr;
/* Configure the Rx flow */
if ((gRxFlowHnd = Cppi_configureRxFlow (gCpdmaHnd, &rxFlowCfg, &isAllocated)) == NULL)
{
uart_write ("Error configuring Rx flow \n");
return -1;
}
else
{
//platform_write("Rx flow configured. handle %p Id %d \n",gRxFlowHnd,Cppi_getFlowId (gRxFlowHnd));
}
/* All done with Rx configuration. Return success. */
return 0;
}
static void configureRxFlow(int fftc_ix){
uint8_t isAllocated;
int rxQueue, freeRxQueue;
Cppi_RxFlowCfg rxFlowCfg;
switch(fftc_ix){
case 0:
rxQueue = QUEUE_RX_FFTC_A;
freeRxQueue = QUEUE_FREE_RX_FFTC_A;
break;
case 1:
rxQueue = QUEUE_RX_FFTC_B;
freeRxQueue = QUEUE_FREE_RX_FFTC_B;
break;
}
/* Initialize the flow configuration */
memset (&rxFlowCfg, 0, sizeof(Cppi_RxFlowCfg));
/* Setup a Rx Flow for this Rx object */
rxFlowCfg.flowIdNum = 0;
rxFlowCfg.rx_dest_qmgr = 0;
rxFlowCfg.rx_dest_qnum = rxQueue;
rxFlowCfg.rx_desc_type = Cppi_DescType_HOST;
rxFlowCfg.rx_ps_location = Cppi_PSLoc_PS_IN_DESC;
rxFlowCfg.rx_psinfo_present = 0;
rxFlowCfg.rx_error_handling = 0; /* Drop the packet, do not retry on starvation by default */
rxFlowCfg.rx_einfo_present = 0; /* By default no EPIB info */
rxFlowCfg.rx_dest_tag_lo_sel = 4; /* Always pick the dest tag 7:0 bits from the PD dest_tag */
rxFlowCfg.rx_dest_tag_hi_sel = 5; /* Always pick the dest tag 15:8 bits from the PD dest_tag */
rxFlowCfg.rx_src_tag_lo_sel = 2; /* Always pick the src tag 7:0 bits from the PD flow_id 7:0 */
rxFlowCfg.rx_src_tag_hi_sel = 4; /* Always pick the src tag 15:8 bits from the PD src_tag 7:0 */
/* By default, we disable Rx Thresholds */
rxFlowCfg.rx_size_thresh0_en = 0;
rxFlowCfg.rx_size_thresh1_en = 0;
rxFlowCfg.rx_size_thresh2_en = 0;
rxFlowCfg.rx_size_thresh0 = 0x0;
rxFlowCfg.rx_size_thresh1 = 0x0;
rxFlowCfg.rx_size_thresh2 = 0x0;
rxFlowCfg.rx_fdq0_sz0_qmgr = 0; /* Setup the Receive free queue for the flow */
rxFlowCfg.rx_fdq0_sz0_qnum = freeRxQueue;
rxFlowCfg.rx_fdq0_sz1_qnum = 0x0;
rxFlowCfg.rx_fdq0_sz1_qmgr = 0x0;
rxFlowCfg.rx_fdq0_sz2_qnum = 0x0;
rxFlowCfg.rx_fdq0_sz2_qmgr = 0x0;
rxFlowCfg.rx_fdq0_sz3_qnum = 0x0;
rxFlowCfg.rx_fdq0_sz3_qmgr = 0x0;
rxFlowCfg.rx_fdq1_qnum = freeRxQueue; /* Use the Rx Queue to pick descriptors */
rxFlowCfg.rx_fdq1_qmgr = 0;
rxFlowCfg.rx_fdq2_qnum = freeRxQueue; /* Use the Rx Queue to pick descriptors */
rxFlowCfg.rx_fdq2_qmgr = 0;
rxFlowCfg.rx_fdq3_qnum = freeRxQueue; /* Use the Rx Queue to pick descriptors */
rxFlowCfg.rx_fdq3_qmgr = 0;
/* Configure the Rx flow */
if ((hCppiRxFlow[fftc_ix] = Cppi_configureRxFlow (hCppi[fftc_ix], &rxFlowCfg, &isAllocated)) == NULL){
printf ("Error configuring Rx flow \n");
}
}
