// CForceChartDlg 消息处理程序
void CForceChartDlg::receive_data()
{
for (int i=0;i<4;i++)
{
DAQ("Dev1",i);
RD[i]=G0[5];
}
}
//////////////////////////// MAIN //////////////////// MAIN //////////////
int main()
{
// Local Variables for main()
int i = 0; // index
int menusel = 99999; // Menu Select
int mode = 9; // Mode of Operation
int enable_state = 0; // 0: disabled, 1: enabled
int thres = 0; // Trigger Threshold
char updateint = 'N'; // switch to change integral values
u32 databuff = 0; // size of the data buffer
// Initialize System
init_platform(); // This initializes the platform, which is ...
ps7_post_config();
Xil_DCacheDisable(); //
InitializeAXIDma(); // Initialize the AXI DMA Transfer Interface
Xil_Out32 (XPAR_AXI_GPIO_16_BASEADDR, 16384);
Xil_Out32 (XPAR_AXI_GPIO_17_BASEADDR , 1);
InitializeInterruptSystem(XPAR_PS7_SCUGIC_0_DEVICE_ID);
for (i=0; i<32; i++ ) { RecvBuffer[i] = '_'; } // Clear RecvBuffer Variable
for (i=0; i<32; i++ ) { SendBuffer[i] = '_'; } // Clear SendBuffer Variable
//*******************Setup the UART **********************//
XUartPs_Config *Config = XUartPs_LookupConfig(UART_DEVICEID);
if (NULL == Config) { return 1;}
Status = XUartPs_CfgInitialize(&Uart_PS, Config, Config->BaseAddress);
if (Status != 0){ return 1; }
/* Conduct a Selftest for the UART */
Status = XUartPs_SelfTest(&Uart_PS);
if (Status != 0) { return 1; }
/* Set to normal mode. */
XUartPs_SetOperMode(&Uart_PS, XUARTPS_OPER_MODE_NORMAL);
//*******************Setup the UART **********************//
//*******************Receive and Process Packets **********************//
Xil_Out32 (XPAR_AXI_GPIO_0_BASEADDR, 11);
Xil_Out32 (XPAR_AXI_GPIO_1_BASEADDR, 71);
Xil_Out32 (XPAR_AXI_GPIO_2_BASEADDR, 167);
Xil_Out32 (XPAR_AXI_GPIO_3_BASEADDR, 2015);
Xil_Out32 (XPAR_AXI_GPIO_4_BASEADDR, 12);
Xil_Out32 (XPAR_AXI_GPIO_5_BASEADDR, 75);
Xil_Out32 (XPAR_AXI_GPIO_6_BASEADDR, 75);
Xil_Out32 (XPAR_AXI_GPIO_7_BASEADDR, 5);
Xil_Out32 (XPAR_AXI_GPIO_8_BASEADDR, 25);
//*******************Receive and Process Packets **********************//
//******************Setup Detector and Module Objects*****************//
//LDetector *Detector = LDetector();
//Detector->SetMode(1); // Processed Data Mode
//******************Setup Detector and Module Objects*****************//
// *********** Setup the Hardware Reset GPIO ****************//
GPIOConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
Status = XGpioPs_CfgInitialize(&Gpio, GPIOConfigPtr, GPIOConfigPtr ->BaseAddr);
if (Status != XST_SUCCESS) { return XST_FAILURE; }
XGpioPs_SetDirectionPin(&Gpio, SW_BREAK_GPIO, 1);
// *********** Setup the Hardware Reset MIO ****************//
// ******************* POLLING LOOP *******************//
xil_printf("\n\r Turn on Local Echo: under Terminal-Setup in Tera Term \n\r");
xil_printf(" Code is expecting a 'Return' after Each Command \n\r");
while(1){
sw = 0; // stop switch reset to 0
XUartPs_SetOptions(&Uart_PS,XUARTPS_OPTION_RESET_RX); // Clear UART Read Buffer
for (i=0; i<32; i++ ) { RecvBuffer[i] = '_'; } // Clear RecvBuffer Variable
sleep(0.5); // Built in Latency ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 0.5 s
xil_printf("\n\r MAIN MENU \n\r");
xil_printf("******************************\n\r");
xil_printf(" 0) Set Mode of Operation\n\r");
xil_printf(" 1) Enable or disable the system\n\r");
xil_printf(" 2) Continuously Read of Processed Data\n\r");
xil_printf("\n\r **Setup Parameters ** \n\r");
xil_printf(" 3) Set Trigger Threshold\n\r");
xil_printf(" 4) Set Integration Times (number of clock cycles * 4ns) \n\r");
xil_printf("\n\r ** Additional Commands ** \n\r");
xil_printf(" 5) Perform a DMA transfer of Waveform Data\n\r");
xil_printf(" 6) Perform a DMA transfer of Processed Data\n\r");
xil_printf(" 7) Check the Size of the Data Buffered (Max = 4095) \n\r");
xil_printf(" 8) Clear the Processed Data Buffers\n\r");
xil_printf(" 9) Execute Print of Data on DRAM \n\r");
xil_printf("******************************\n\n\r");
while (XUartPs_IsSending(&Uart_PS)) {i++;} // Wait until Write Buffer is Sent
// Wait for Input, Check
// If input is valid break while and enter case statement
// If input is invalid break and try again
ReadCommandPoll();
menusel = 99999;
sscanf(RecvBuffer,"%01d",&menusel);
if ( menusel < 0 || menusel > 9 ) {
xil_printf(" Invalid Command: Enter 0-9 \n\r");
sleep(1); // Built in Latency ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 s
}
switch (menusel) { // Switch-Case Menu Select
case 0: //Set Mode of Operation
mode = 99; //Detector->GetMode();
xil_printf("\n\r Waveform Data: \t Enter 0 <return>\n\r");
xil_printf(" LPF Waveform Data: \t Enter 1 <return>\n\r");
xil_printf(" DFF Waveform Data: \t Enter 2 <return>\n\r");
xil_printf(" TRG Waveform Data: \t Enter 3 <return>\n\r");
xil_printf(" Processed Data: \t Enter 4 <return>\n\r");
ReadCommandPoll();
sscanf(RecvBuffer,"%01d",&mode);
if (mode < 0 || mode > 4 ) { xil_printf("Invalid Command\n\r"); break; }
// mode = 0, AA waveform
// mode = 1, LPF waveform
// mode = 2, DFF waveform
// mode = 3, TRG waveform
// mode = 4, Processed Data
//Detector->SetMode(mode); // Set Mode for Detector
Xil_Out32 (XPAR_AXI_GPIO_14_BASEADDR, ((u32)mode));
// Register 14
if ( mode == 0 ) { xil_printf("Transfer AA Waveforms\n\r"); }
if ( mode == 1 ) { xil_printf("Transfer LPF Waveforms\n\r"); }
if ( mode == 2 ) { xil_printf("Transfer DFF Waveforms\n\r"); }
if ( mode == 3 ) { xil_printf("Transfer TRG Waveforms\n\r"); }
if ( mode == 4 ) { xil_printf("Transfer Processed Data\n\r"); }
sleep(1); // Built in Latency ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 s
break;
case 1: //Enable or disable the system
xil_printf("\n\r Disable: Enter 0 <return>\n\r");
xil_printf(" Enable: Enter 1 <return>\n\r");
ReadCommandPoll();
sscanf(RecvBuffer,"%01d",&enable_state);
if (enable_state != 0 && enable_state != 1) { xil_printf("Invalid Command\n\r"); break; }
Xil_Out32(XPAR_AXI_GPIO_18_BASEADDR, ((u32)enable_state));
// Register 18 Out enabled, In Disabled
if ( enable_state == 1 ) { xil_printf("DAQ Enabled\n\r"); }
if ( enable_state == 0 ) { xil_printf("DAQ Disabled\n\r"); }
sleep(1); // Built in Latency ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 s
break;
case 2: //Continuously Read of Processed Data
xil_printf("\n\r ********Data Acquisition:\n\r");
xil_printf(" Press 'q' to Stop or Press Hardware USR reset button \n\r");
xil_printf(" Press <return> to Start");
ReadCommandPoll();
DAQ();
sw = 0; // broke out of the read loop, stop swith reset to 0
break;
case 3: //Set Threshold
xil_printf("\n\r Existing Threshold = %d \n\r",Xil_In32(XPAR_AXI_GPIO_10_BASEADDR));
xil_printf(" Enter Threshold (6144 to 10240) <return> \n\r");
ReadCommandPoll();
sscanf(RecvBuffer,"%04d",&thres);
Xil_Out32(XPAR_AXI_GPIO_10_BASEADDR, ((u32)thres));
xil_printf("New Threshold = %d \n\r",Xil_In32(XPAR_AXI_GPIO_10_BASEADDR));
sleep(1); // Built in Latency ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 s
break;
case 4: //Set Integration Times
xil_printf("\n\r Existing Integration Times \n\r");
xil_printf(" Time = 0 ns is when the Pulse Crossed Threshold \n\r");
xil_printf(" Baseline Integral Window \t [-200ns,%dns] \n\r",-52 + ((int)Xil_In32(XPAR_AXI_GPIO_0_BASEADDR))*4 );
xil_printf(" Short Integral Window \t [-200ns,%dns] \n\r",-52 + ((int)Xil_In32(XPAR_AXI_GPIO_1_BASEADDR))*4 );
xil_printf(" Long Integral Window \t [-200ns,%dns] \n\r",-52 + ((int)Xil_In32(XPAR_AXI_GPIO_2_BASEADDR))*4 );
xil_printf(" Full Integral Window \t [-200ns,%dns] \n\r",-52 + ((int)Xil_In32(XPAR_AXI_GPIO_3_BASEADDR))*4 );
xil_printf(" Change: (Y)es (N)o <return>\n\r");
ReadCommandPoll();
sscanf(RecvBuffer,"%c",&updateint);
if (updateint == 'N' || updateint == 'n') { break; }
if (updateint == 'Y' || updateint == 'y') { SetIntegrationTimes(0); }
sleep(1); // Built in Latency ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 s
break;
case 5: //Perform a DMA transfer
xil_printf("\n\r Perform DMA Transfer of Waveform Data\n\r");
xil_printf(" Press 'q' to Exit Transfer \n\r");
Xil_Out32 (XPAR_AXI_DMA_0_BASEADDR + 0x48, 0xa000000);
Xil_Out32 (XPAR_AXI_DMA_0_BASEADDR + 0x58 , 65536);
sleep(1); // Built in Latency ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 s
PrintData(); // Display data to console.
sw = 0; // broke out of the read loop, stop swith reset to 0
break;
case 6: //Perform a DMA transfer of Processed data
xil_printf("\n\r ********Perform DMA Transfer of Processed Data \n\r");
xil_printf(" Press 'q' to Exit Transfer \n\r");
//Xil_Out32 (XPAR_AXI_GPIO_18_BASEADDR, 0); // Disable : GPIO Reg Capture Module
Xil_Out32 (XPAR_AXI_GPIO_15_BASEADDR, 1); // Enable: GPIO Reg to Readout Data MUX
//sleep(1); // Built in Latency ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 s
Xil_Out32 (XPAR_AXI_DMA_0_BASEADDR + 0x48, 0xa000000); // Transfer from BRAM to DRAM, start address 0xa000000, 16-bit length
Xil_Out32 (XPAR_AXI_DMA_0_BASEADDR + 0x58 , 65536);
sleep(1); // Built in Latency ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 s
Xil_Out32 (XPAR_AXI_GPIO_15_BASEADDR, 0); // Disable: GPIO Reg turn off Readout Data MUX
ClearBuffers();
PrintData(); // Display data to console.
//Xil_Out32 (XPAR_AXI_GPIO_18_BASEADDR, 1); // Enable : GPIO Reg Capture Module
sw = 0; // broke out of the read loop, stop swith reset to 0
sleep(1); // Built in Latency ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 s
break;
case 7: //Check the Size of the Data Buffers
databuff = Xil_In32 (XPAR_AXI_GPIO_11_BASEADDR);
xil_printf("\n\r BRAM Data Buffer Size = %d \n\r",databuff);
sleep(1); // Built in Latency ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 s
break;
case 8: //Clear the processed data buffers
xil_printf("\n\r Clear the Data Buffers\n\r");
ClearBuffers();
sleep(1); // Built in Latency ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 s
break;
case 9: //Print DMA Data
xil_printf("\n\r Print Data\n\r");
PrintData();
break;
default :
break;
} // End Switch-Case Menu Select
} // ******************* POLLING LOOP *******************//
cleanup_platform(); // Clean up the platform, which is ...
return 0;
}