/*
* Setup MBUS dram target info.
*/
void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
const u32 ddr_window_cpu_base)
{
void __iomem *addr;
int i;
int cs;
orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
addr = (void __iomem *)ddr_window_cpu_base;
for (i = 0, cs = 0; i < 4; i++) {
u32 base = readl(addr + DDR_BASE_CS_OFF(i));
u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
/*
* Chip select enabled?
*/
if (size & 1) {
struct mbus_dram_window *w;
w = &orion_mbus_dram_info.cs[cs++];
w->cs_index = i;
w->mbus_attr = 0xf & ~(1 << i);
w->base = base & 0xffff0000;
w->size = (size | 0x0000ffff) + 1;
}
}
orion_mbus_dram_info.num_cs = cs;
}
void __init kirkwood_setup_cpu_mbus(void)
{
void __iomem *addr;
int i;
int cs;
for (i = 0; i < 8; i++) {
addr = (void __iomem *)WIN_OFF(i);
writel(0, addr + WIN_BASE_OFF);
writel(0, addr + WIN_CTRL_OFF);
if (cpu_win_can_remap(i)) {
writel(0, addr + WIN_REMAP_LO_OFF);
writel(0, addr + WIN_REMAP_HI_OFF);
}
}
setup_cpu_win(0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE,
TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE);
setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE);
setup_cpu_win(2, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
TARGET_DEV_BUS, ATTR_DEV_NAND, -1);
setup_cpu_win(3, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
TARGET_SRAM, ATTR_SRAM, -1);
kirkwood_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
addr = (void __iomem *)DDR_WINDOW_CPU_BASE;
for (i = 0, cs = 0; i < 4; i++) {
u32 base = readl(addr + DDR_BASE_CS_OFF(i));
u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
if (size & 1) {
struct mbus_dram_window *w;
w = &kirkwood_mbus_dram_info.cs[cs++];
w->cs_index = i;
w->mbus_attr = 0xf & ~(1 << i);
w->base = base & 0xffff0000;
w->size = (size | 0x0000ffff) + 1;
}
}
kirkwood_mbus_dram_info.num_cs = cs;
}
void __init mv78xx0_setup_cpu_mbus(void)
{
void __iomem *addr;
int i;
int cs;
for (i = 0; i < 14; i++) {
addr = win_cfg_base(i);
writel(0, addr + WIN_BASE_OFF);
writel(0, addr + WIN_CTRL_OFF);
if (cpu_win_can_remap(i)) {
writel(0, addr + WIN_REMAP_LO_OFF);
writel(0, addr + WIN_REMAP_HI_OFF);
}
}
mv78xx0_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
if (mv78xx0_core_index() == 0)
addr = (void __iomem *)DDR_WINDOW_CPU0_BASE;
else
addr = (void __iomem *)DDR_WINDOW_CPU1_BASE;
for (i = 0, cs = 0; i < 4; i++) {
u32 base = readl(addr + DDR_BASE_CS_OFF(i));
u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
if (size & 1) {
struct mbus_dram_window *w;
w = &mv78xx0_mbus_dram_info.cs[cs++];
w->cs_index = i;
w->mbus_attr = 0xf & ~(1 << i);
w->base = base & 0xffff0000;
w->size = (size | 0x0000ffff) + 1;
}
}
mv78xx0_mbus_dram_info.num_cs = cs;
}
