return 0; } if (n < 32) { /* GP regs */ env->regs[n] = ldl_p(mem_buf); } else if (n == 32) { /* PC */ env->regs[R_PC] = ldl_p(mem_buf); } else if (n < 49) { /* Status regs */ env->regs[n - 1] = ldl_p(mem_buf); } return 4; } static Property nios2_properties[] = { DEFINE_PROP_BOOL("mmu_present", Nios2CPU, mmu_present, true), /* ALTR,pid-num-bits */ DEFINE_PROP_UINT32("mmu_pid_num_bits", Nios2CPU, pid_num_bits, 8), /* ALTR,tlb-num-ways */ DEFINE_PROP_UINT32("mmu_tlb_num_ways", Nios2CPU, tlb_num_ways, 16), /* ALTR,tlb-num-entries */ DEFINE_PROP_UINT32("mmu_pid_num_entries", Nios2CPU, tlb_num_entries, 256), DEFINE_PROP_END_OF_LIST(), }; static void nios2_cpu_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); CPUClass *cc = CPU_CLASS(oc); Nios2CPUClass *ncc = NIOS2_CPU_CLASS(oc);
* equivalent). */ s->irq_reset_nonsecure = true; } } static Property arm_gic_common_properties[] = { DEFINE_PROP_UINT32("num-cpu", GICState, num_cpu, 1), DEFINE_PROP_UINT32("num-irq", GICState, num_irq, 32), /* Revision can be 1 or 2 for GIC architecture specification * versions 1 or 2, or 0 to indicate the legacy 11MPCore GIC. * (Internally, 0xffffffff also indicates "not a GIC but an NVIC".) */ DEFINE_PROP_UINT32("revision", GICState, revision, 1), /* True if the GIC should implement the security extensions */ DEFINE_PROP_BOOL("has-security-extensions", GICState, security_extn, 0), DEFINE_PROP_END_OF_LIST(), }; static void arm_gic_common_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass); dc->reset = arm_gic_common_reset; dc->realize = arm_gic_common_realize; dc->props = arm_gic_common_properties; dc->vmsd = &vmstate_gic; albifc->arm_linux_init = arm_gic_common_linux_init; }
bool ps_enable; /* IRQ to pulse out when present timer hits zero */ qemu_irq hit_out; /* State var to remember hit_in level */ bool ps_level; QEMUBH *bh; ptimer_state *ptimer; uint32_t regs[R_MAX]; RegisterInfo regs_info[R_MAX]; const char *prefix; } XilinxPIT; static Property xlx_iom_properties[] = { DEFINE_PROP_UINT32("frequency", XilinxPIT, frequency, 66*1000000), DEFINE_PROP_BOOL("use-pit", XilinxPIT, cfg.use, 0), DEFINE_PROP_UINT32("pit-size", XilinxPIT, cfg.size, 1), DEFINE_PROP_BOOL("pit-readable", XilinxPIT, cfg.readable, 1), DEFINE_PROP_BOOL("pit-interrupt", XilinxPIT, cfg.interrupt, 0), DEFINE_PROP_END_OF_LIST(), }; static uint64_t pit_ctr_pr(RegisterInfo *reg, uint64_t val) { XilinxPIT *s = XILINX_IO_MODULE_PIT(reg->opaque); uint32_t r; if (!s->cfg.use) { qemu_log_mask(LOG_GUEST_ERROR, "%s: Disabled\n", s->prefix); return 0xdeadbeef; }
.read_data = scsi_read_data, .write_data = scsi_write_data, .get_buf = scsi_get_buf, .load_request = scsi_generic_load_request, .save_request = scsi_generic_save_request, }; static SCSIRequest *scsi_new_request(SCSIDevice *d, uint32_t tag, uint32_t lun, uint8_t *buf, void *hba_private) { return scsi_req_alloc(&scsi_generic_req_ops, d, tag, lun, hba_private); } static Property scsi_generic_properties[] = { DEFINE_PROP_DRIVE("drive", SCSIDevice, conf.blk), DEFINE_PROP_BOOL("share-rw", SCSIDevice, conf.share_rw, false), DEFINE_PROP_END_OF_LIST(), }; static int scsi_generic_parse_cdb(SCSIDevice *dev, SCSICommand *cmd, uint8_t *buf, void *hba_private) { return scsi_bus_parse_cdb(dev, cmd, buf, hba_private); } static void scsi_generic_class_initfn(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); SCSIDeviceClass *sc = SCSI_DEVICE_CLASS(klass); sc->realize = scsi_generic_realize;
} static void console_reset(DeviceState *dev) { SCLPEvent *event = SCLP_EVENT(dev); SCLPConsoleLM *scon = SCLPLM_CONSOLE(event); event->event_pending = false; scon->length = 0; scon->write_errors = 0; } static Property console_properties[] = { DEFINE_PROP_CHR("chardev", SCLPConsoleLM, chr), DEFINE_PROP_UINT32("write_errors", SCLPConsoleLM, write_errors, 0), DEFINE_PROP_BOOL("echo", SCLPConsoleLM, echo, true), DEFINE_PROP_END_OF_LIST(), }; static void console_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); SCLPEventClass *ec = SCLP_EVENT_CLASS(klass); dc->props = console_properties; dc->reset = console_reset; dc->vmsd = &vmstate_sclplmconsole; ec->init = console_init; ec->get_send_mask = send_mask; ec->get_receive_mask = receive_mask; ec->can_handle_event = can_handle_event;
* QEMUs relying on it don't break. */ ipl->compat_start_addr = ipl->start_addr; ipl->compat_bios_start_addr = ipl->bios_start_addr; qemu_register_reset(qdev_reset_all_fn, dev); error: error_propagate(errp, err); } static Property s390_ipl_properties[] = { DEFINE_PROP_STRING("kernel", S390IPLState, kernel), DEFINE_PROP_STRING("initrd", S390IPLState, initrd), DEFINE_PROP_STRING("cmdline", S390IPLState, cmdline), DEFINE_PROP_STRING("firmware", S390IPLState, firmware), DEFINE_PROP_STRING("netboot_fw", S390IPLState, netboot_fw), DEFINE_PROP_BOOL("enforce_bios", S390IPLState, enforce_bios, false), DEFINE_PROP_BOOL("iplbext_migration", S390IPLState, iplbext_migration, true), DEFINE_PROP_END_OF_LIST(), }; static void s390_ipl_set_boot_menu(S390IPLState *ipl) { QemuOptsList *plist = qemu_find_opts("boot-opts"); QemuOpts *opts = QTAILQ_FIRST(&plist->head); uint8_t *flags = &ipl->qipl.qipl_flags; uint32_t *timeout = &ipl->qipl.boot_menu_timeout; const char *tmp; unsigned long splash_time = 0; if (!get_boot_device(0)) {
XilinxPCIEHost *s = XILINX_PCIE_HOST(obj); XilinxPCIERoot *root = &s->root; object_initialize(root, sizeof(*root), TYPE_XILINX_PCIE_ROOT); object_property_add_child(obj, "root", OBJECT(root), NULL); qdev_prop_set_int32(DEVICE(root), "addr", PCI_DEVFN(0, 0)); qdev_prop_set_bit(DEVICE(root), "multifunction", false); } static Property xilinx_pcie_host_props[] = { DEFINE_PROP_UINT32("bus_nr", XilinxPCIEHost, bus_nr, 0), DEFINE_PROP_SIZE("cfg_base", XilinxPCIEHost, cfg_base, 0), DEFINE_PROP_SIZE("cfg_size", XilinxPCIEHost, cfg_size, 32 * MiB), DEFINE_PROP_SIZE("mmio_base", XilinxPCIEHost, mmio_base, 0), DEFINE_PROP_SIZE("mmio_size", XilinxPCIEHost, mmio_size, 1 * MiB), DEFINE_PROP_BOOL("link_up", XilinxPCIEHost, link_up, true), DEFINE_PROP_END_OF_LIST(), }; static void xilinx_pcie_host_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); hc->root_bus_path = xilinx_pcie_host_root_bus_path; dc->realize = xilinx_pcie_host_realize; set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); dc->fw_name = "pci"; dc->props = xilinx_pcie_host_props; }
* picky DTB consumer will also provide a helpful error message. */ cpu->dtb_compatible = "qemu,unknown"; cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; if (tcg_enabled() && !inited) { inited = true; arm_translate_init(); } } static Property arm_cpu_reset_cbar_property = DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); static Property arm_cpu_reset_hivecs_property = DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); static Property arm_cpu_rvbar_property = DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); static void arm_cpu_post_init(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, &error_abort); } if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
.version_id = 1, .minimum_version_id = 1, .post_load = pcie_cap_slot_post_load, .fields = (VMStateField[]) { VMSTATE_PCI_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot), VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log, PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog), VMSTATE_MSIX_TEST(parent_obj.parent_obj.parent_obj.parent_obj, GenPCIERootPort, gen_rp_test_migrate_msix), VMSTATE_END_OF_LIST() } }; static Property gen_rp_props[] = { DEFINE_PROP_BOOL("x-migrate-msix", GenPCIERootPort, migrate_msix, true), DEFINE_PROP_UINT32("bus-reserve", GenPCIERootPort, res_reserve.bus, -1), DEFINE_PROP_SIZE("io-reserve", GenPCIERootPort, res_reserve.io, -1), DEFINE_PROP_SIZE("mem-reserve", GenPCIERootPort, res_reserve.mem_non_pref, -1), DEFINE_PROP_SIZE("pref32-reserve", GenPCIERootPort, res_reserve.mem_pref_32, -1), DEFINE_PROP_SIZE("pref64-reserve", GenPCIERootPort, res_reserve.mem_pref_64, -1), DEFINE_PROP_PCIE_LINK_SPEED("x-speed", PCIESlot, speed, PCIE_LINK_SPEED_16), DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot, width, PCIE_LINK_WIDTH_32), DEFINE_PROP_END_OF_LIST()
set_float_rounding_mode(float_round_nearest_even, &env->fp_status); #ifndef CONFIG_USER_ONLY /* Inbound IRQ and FIR lines */ qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2); #endif } static const VMStateDescription vmstate_mb_cpu = { .name = "cpu", .unmigratable = 1, }; static Property mb_properties[] = { DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0), DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot, false), /* If use-fpu > 0 - FPU is enabled * If use-fpu = 2 - Floating point conversion and square root instructions * are enabled */ DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2), /* If use-hw-mul > 0 - Multiplier is enabled * If use-hw-mul = 2 - 64-bit multiplier is enabled */ DEFINE_PROP_UINT8("use-hw-mul", MicroBlazeCPU, cfg.use_hw_mul, 2), DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true), DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true), DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true), DEFINE_PROP_BOOL("use-pcmp-instr", MicroBlazeCPU, cfg.use_pcmp_instr, true), DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true), DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
.minimum_version_id_old = 1, .fields = (VMStateField[]) { VMSTATE_UINT32(dr, IMXGPIOState), VMSTATE_UINT32(gdir, IMXGPIOState), VMSTATE_UINT32(psr, IMXGPIOState), VMSTATE_UINT64(icr, IMXGPIOState), VMSTATE_UINT32(imr, IMXGPIOState), VMSTATE_UINT32(isr, IMXGPIOState), VMSTATE_BOOL(has_edge_sel, IMXGPIOState), VMSTATE_UINT32(edge_sel, IMXGPIOState), VMSTATE_END_OF_LIST() } }; static Property imx_gpio_properties[] = { DEFINE_PROP_BOOL("has-edge-sel", IMXGPIOState, has_edge_sel, true), DEFINE_PROP_BOOL("has-upper-pin-irq", IMXGPIOState, has_upper_pin_irq, false), DEFINE_PROP_END_OF_LIST(), }; static void imx_gpio_reset(DeviceState *dev) { IMXGPIOState *s = IMX_GPIO(dev); s->dr = 0; s->gdir = 0; s->psr = 0; s->icr = 0; s->imr = 0; s->isr = 0;
err_unrealize: while (--j >= 0) { spapr_unrealize_vcpu(sc->threads[j], sc); } err: while (--i >= 0) { spapr_delete_vcpu(sc->threads[i], sc); } g_free(sc->threads); error_propagate(errp, local_err); } static Property spapr_cpu_core_properties[] = { DEFINE_PROP_INT32("node-id", SpaprCpuCore, node_id, CPU_UNSET_NUMA_NODE_ID), DEFINE_PROP_BOOL("pre-3.0-migration", SpaprCpuCore, pre_3_0_migration, false), DEFINE_PROP_END_OF_LIST() }; static void spapr_cpu_core_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc); dc->realize = spapr_cpu_core_realize; dc->unrealize = spapr_cpu_core_unrealize; dc->props = spapr_cpu_core_properties; scc->cpu_type = data; } #define DEFINE_SPAPR_CPU_CORE_TYPE(cpu_model) \
qdev_init_nofail(dev); /* Create bus on bridge device */ bus = qbus_create(TYPE_VIRTUAL_CSS_BUS, dev, "virtual-css"); cbus = VIRTUAL_CSS_BUS(bus); /* Enable hotplugging */ qbus_set_hotplug_handler(bus, dev, &error_abort); return cbus; } /***************** Virtual-css Bus Bridge Device ********************/ static Property virtual_css_bridge_properties[] = { DEFINE_PROP_BOOL("css_dev_path", VirtualCssBridge, css_dev_path, true), DEFINE_PROP_END_OF_LIST(), }; static void virtual_css_bridge_class_init(ObjectClass *klass, void *data) { HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); DeviceClass *dc = DEVICE_CLASS(klass); hc->unplug = ccw_device_unplug; set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); dc->props = virtual_css_bridge_properties; } static const TypeInfo virtual_css_bridge_info = { .name = TYPE_VIRTUAL_CSS_BRIDGE,
s->data = cpu_to_be64(s->data); } else { s->data = cpu_to_le64(s->data); } } static void generic_loader_unrealize(DeviceState *dev, Error **errp) { qemu_unregister_reset(generic_loader_reset, dev); } static Property generic_loader_props[] = { DEFINE_PROP_UINT64("addr", GenericLoaderState, addr, 0), DEFINE_PROP_UINT64("data", GenericLoaderState, data, 0), DEFINE_PROP_UINT8("data-len", GenericLoaderState, data_len, 0), DEFINE_PROP_BOOL("data-be", GenericLoaderState, data_be, false), /* Xilinx: This is the old deprecated command line argument. It will be * removed in the future. */ DEFINE_PROP_UINT32("cpu", GenericLoaderState, cpu_num_dep, CPU_NONE), DEFINE_PROP_UINT32("cpu-num", GenericLoaderState, cpu_num, CPU_NONE), DEFINE_PROP_BOOL("force-raw", GenericLoaderState, force_raw, false), DEFINE_PROP_STRING("file", GenericLoaderState, file), DEFINE_PROP_END_OF_LIST(), }; static void generic_loader_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); /* The reset function is not registered here and is instead registered in
VMSTATE_UINT32(maccr, Ftgmac100State), VMSTATE_UINT32(phycr, Ftgmac100State), VMSTATE_UINT32(phydata, Ftgmac100State), VMSTATE_UINT32(aptcr, Ftgmac100State), VMSTATE_UINT32(phy_status, Ftgmac100State), VMSTATE_UINT32(phy_control, Ftgmac100State), VMSTATE_UINT32(phy_advertise, Ftgmac100State), VMSTATE_UINT32(phy_int, Ftgmac100State), VMSTATE_UINT32(phy_int_mask, Ftgmac100State), VMSTATE_END_OF_LIST() } }; static Property ftgmac100_properties[] = { DEFINE_PROP_BOOL("aspeed", Ftgmac100State, aspeed, false), DEFINE_NIC_PROPERTIES(Ftgmac100State, conf), DEFINE_PROP_END_OF_LIST(), }; static void ftgmac100_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->vmsd = &vmstate_ftgmac100; dc->reset = ftgmac100_reset; dc->props = ftgmac100_properties; set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); dc->realize = ftgmac100_realize; dc->desc = "Faraday FTGMAC100 Gigabit Ethernet emulation"; }
*/ stq_p(rom_ptr(INITRD_PARM_START), initrd_offset); stq_p(rom_ptr(INITRD_PARM_SIZE), initrd_size); } } qemu_register_reset(qdev_reset_all_fn, dev); error: error_propagate(errp, err); } static Property s390_ipl_properties[] = { DEFINE_PROP_STRING("kernel", S390IPLState, kernel), DEFINE_PROP_STRING("initrd", S390IPLState, initrd), DEFINE_PROP_STRING("cmdline", S390IPLState, cmdline), DEFINE_PROP_STRING("firmware", S390IPLState, firmware), DEFINE_PROP_BOOL("enforce_bios", S390IPLState, enforce_bios, false), DEFINE_PROP_END_OF_LIST(), }; /* * In addition to updating the iplstate, this function returns: * - 0 if system was ipled with external kernel * - -1 if no valid boot device was found * - ccw id of the boot device otherwise */ static uint64_t s390_update_iplstate(S390IPLState *ipl) { DeviceState *dev_st; if (ipl->iplb_valid) { ipl->cssid = 0;
}; static void adb_device_realizefn(DeviceState *dev, Error **errp) { ADBDevice *d = ADB_DEVICE(dev); ADBBusState *bus = ADB_BUS(qdev_get_parent_bus(dev)); if (bus->nb_devices >= MAX_ADB_DEVICES) { return; } bus->devices[bus->nb_devices++] = d; } static Property adb_device_properties[] = { DEFINE_PROP_BOOL("disable-direct-reg3-writes", ADBDevice, disable_direct_reg3_writes, false), DEFINE_PROP_END_OF_LIST(), }; static void adb_device_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); dc->realize = adb_device_realizefn; dc->props = adb_device_properties; dc->bus_type = TYPE_ADB_BUS; } static const TypeInfo adb_device_type_info = { .name = TYPE_ADB_DEVICE, .parent = TYPE_DEVICE,
.minimum_version_id_old = 1, .fields = (VMStateField[]) { VMSTATE_UINT32(dr, IMXGPIOState), VMSTATE_UINT32(gdir, IMXGPIOState), VMSTATE_UINT32(psr, IMXGPIOState), VMSTATE_UINT64(icr, IMXGPIOState), VMSTATE_UINT32(imr, IMXGPIOState), VMSTATE_UINT32(isr, IMXGPIOState), VMSTATE_BOOL(has_edge_sel, IMXGPIOState), VMSTATE_UINT32(edge_sel, IMXGPIOState), VMSTATE_END_OF_LIST() } }; static Property imx_gpio_properties[] = { DEFINE_PROP_BOOL("has-edge-sel", IMXGPIOState, has_edge_sel, true), DEFINE_PROP_END_OF_LIST(), }; static void imx_gpio_reset(DeviceState *dev) { IMXGPIOState *s = IMX_GPIO(dev); s->dr = 0; s->gdir = 0; s->psr = 0; s->icr = 0; s->imr = 0; s->isr = 0; s->edge_sel = 0;
return 0; assign_error: /* We get here on assignment failure. Recover by undoing for VQs 0 .. n. */ assert(assign); while (--n >= 0) { virtio_mmio_set_guest_notifier(d, n, !assign, false); } return r; } /* virtio-mmio device */ static Property virtio_mmio_properties[] = { DEFINE_PROP_BOOL("format_transport_address", VirtIOMMIOProxy, format_transport_address, true), DEFINE_PROP_END_OF_LIST(), }; static void virtio_mmio_realizefn(DeviceState *d, Error **errp) { VirtIOMMIOProxy *proxy = VIRTIO_MMIO(d); SysBusDevice *sbd = SYS_BUS_DEVICE(d); qbus_create_inplace(&proxy->bus, sizeof(proxy->bus), TYPE_VIRTIO_MMIO_BUS, d, NULL); sysbus_init_irq(sbd, &proxy->irq); memory_region_init_io(&proxy->iomem, OBJECT(d), &virtio_mem_ops, proxy, TYPE_VIRTIO_MMIO, 0x200); sysbus_init_mmio(sbd, &proxy->iomem); }
rs6000mc_port_list, s, "rs6000mc"); } static const VMStateDescription vmstate_rs6000mc = { .name = "rs6000-mc", .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { VMSTATE_UINT8(port0820_index, RS6000MCState), VMSTATE_END_OF_LIST() }, }; static Property rs6000mc_properties[] = { DEFINE_PROP_UINT32("ram-size", RS6000MCState, ram_size, 0), DEFINE_PROP_BOOL("auto-configure", RS6000MCState, autoconfigure, true), DEFINE_PROP_END_OF_LIST() }; static void rs6000mc_class_initfn(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = rs6000mc_realize; dc->vmsd = &vmstate_rs6000mc; dc->props = rs6000mc_properties; } static const TypeInfo rs6000mc_info = { .name = TYPE_RS6000MC, .parent = TYPE_ISA_DEVICE,
VMSTATE_INT64(timer_expiry, APICCommonState), /* open-coded timer state */ VMSTATE_END_OF_LIST() }, .subsections = (const VMStateDescription*[]) { &vmstate_apic_common_sipi, NULL } }; static Property apic_properties_common[] = { DEFINE_PROP_UINT8("id", APICCommonState, id, -1), DEFINE_PROP_UINT8("version", APICCommonState, version, 0x14), DEFINE_PROP_BIT("vapic", APICCommonState, vapic_control, VAPIC_ENABLE_BIT, true), DEFINE_PROP_BOOL("legacy-instance-id", APICCommonState, legacy_instance_id, false), DEFINE_PROP_END_OF_LIST(), }; static void apic_common_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->reset = apic_reset_common; dc->props = apic_properties_common; dc->realize = apic_common_realize; dc->unrealize = apic_common_unrealize; /* * Reason: APIC and CPU need to be wired up by * x86_cpu_apic_create() */
*/ if (qdev_hotplug) { generic_loader_reset(dev); } } static void generic_loader_unrealize(DeviceState *dev, Error **errp) { qemu_unregister_reset_loader(generic_loader_reset, dev); } static Property generic_loader_props[] = { DEFINE_PROP_UINT64("addr", GenericLoaderState, addr, 0), DEFINE_PROP_UINT64("data", GenericLoaderState, data, 0), DEFINE_PROP_UINT8("data-len", GenericLoaderState, data_len, 0), DEFINE_PROP_BOOL("data-be", GenericLoaderState, data_be, false), DEFINE_PROP_UINT32("cpu-num", GenericLoaderState, cpu_num, CPU_NONE), DEFINE_PROP_BOOL("force-raw", GenericLoaderState, force_raw, false), DEFINE_PROP_STRING("file", GenericLoaderState, file), DEFINE_PROP_UINT16("attrs-requester-id", GenericLoaderState, attrs.requester_id, 0), DEFINE_PROP_BOOL("attrs-debug", GenericLoaderState, attrs.debug, false), DEFINE_PROP_BOOL("attrs-secure", GenericLoaderState, attrs.secure, false), DEFINE_PROP_END_OF_LIST(), }; static void generic_loader_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); /* The reset function is not registered here and is instead registered in
bool use_tx; bool rx_interrupt; bool tx_interrupt; bool err_interrupt; } cfg; CharBackend chr; uint32_t regs[R_MAX_0]; uint32_t baud; DepRegisterInfo regs_info0[R_MAX_0]; DepRegisterInfo regs_info1[R_MAX_1]; DepRegisterInfo *regs_infos[2]; const char *prefix; } XilinxUART; static Property xlx_iom_properties[] = { DEFINE_PROP_BOOL("use-uart-rx", XilinxUART, cfg.use_rx, 0), DEFINE_PROP_BOOL("use-uart-tx", XilinxUART, cfg.use_tx, 0), DEFINE_PROP_BOOL("uart-rx-interrupt", XilinxUART, cfg.rx_interrupt, 0), DEFINE_PROP_BOOL("uart-tx-interrupt", XilinxUART, cfg.tx_interrupt, 0), DEFINE_PROP_BOOL("uart-error-interrupt", XilinxUART, cfg.err_interrupt, 0), DEFINE_PROP_CHR("chardev", XilinxUART, chr), DEFINE_PROP_END_OF_LIST(), }; static void uart_rx(void *opaque, const uint8_t *buf, int size) { XilinxUART *s = opaque; if (!s->cfg.use_rx) { return; }