/* Initialize ethernet interface */ void IP_ENET_Init(IP_ENET_001_Type *LPC_ENET) { /* Enhanced descriptors, burst length = 1 */ LPC_ENET->DMA_BUS_MODE = DMA_BM_ATDS | DMA_BM_PBL(1) | DMA_BM_RPBL(1); /* Initial MAC configuration for checksum offload, full duplex, 100Mbps, disable receive own in half duplex, inter-frame gap of 64-bits */ LPC_ENET->MAC_CONFIG = MAC_CFG_BL(0) | MAC_CFG_IPC | MAC_CFG_DM | MAC_CFG_DO | MAC_CFG_FES | MAC_CFG_PS | MAC_CFG_IFG(3); /* Setup default filter */ LPC_ENET->MAC_FRAME_FILTER = MAC_FF_PR | MAC_FF_RA; /* Flush transmit FIFO */ LPC_ENET->DMA_OP_MODE = DMA_OM_FTF; /* Setup DMA to flush receive FIFOs at 32 bytes, service TX FIFOs at 64 bytes */ LPC_ENET->DMA_OP_MODE |= DMA_OM_RTC(1) | DMA_OM_TTC(0); /* Clear all MAC interrupts */ LPC_ENET->DMA_STAT = DMA_ST_ALL; /* Enable MAC interrupts */ LPC_ENET->DMA_INT_EN = 0; }
/* Basic Ethernet interface initialization */ void Chip_ENET_Init(LPC_ENET_T *pENET) { Chip_Clock_EnableOpts(CLK_MX_ETHERNET, true, true, 1); reset(pENET); /* Setup MII link divider to /102 and PHY address 1 */ Chip_ENET_SetupMII(pENET, 4, 1); /* Enhanced descriptors, burst length = 1 */ pENET->DMA_BUS_MODE = DMA_BM_ATDS | DMA_BM_PBL(1) | DMA_BM_RPBL(1); /* Initial MAC configuration for checksum offload, full duplex, 100Mbps, disable receive own in half duplex, inter-frame gap of 64-bits */ pENET->MAC_CONFIG = MAC_CFG_BL(0) | MAC_CFG_IPC | MAC_CFG_DM | MAC_CFG_DO | MAC_CFG_FES | MAC_CFG_PS | MAC_CFG_IFG(3); /* Setup default filter */ pENET->MAC_FRAME_FILTER = MAC_FF_PR | MAC_FF_RA; /* Flush transmit FIFO */ pENET->DMA_OP_MODE = DMA_OM_FTF; /* Setup DMA to flush receive FIFOs at 32 bytes, service TX FIFOs at 64 bytes */ pENET->DMA_OP_MODE |= DMA_OM_RTC(1) | DMA_OM_TTC(0); /* Clear all MAC interrupts */ pENET->DMA_STAT = DMA_ST_ALL; /* Enable MAC interrupts */ pENET->DMA_INT_EN = 0; }
/** \brief Low level init of the MAC and PHY. * * \param[in] netif Pointer to LWIP netif structure * \return ERR_OK or error code */ static err_t low_level_init(struct netif *netif) { struct lpc_enetdata *lpc_netifdata = netif->state; err_t err; s32_t timeout; /* Enable MAC clocking from same source as CPU */ CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_PERIPHERAL_ETHERNET); /* Slightly different clocking for RMII and MII modes */ CGU_EntityConnect(CGU_CLKSRC_ENET_TX_CLK, CGU_BASE_PHY_TX); #if LPC_EMAC_RMII == 1 /* RMII mode gets PHY RX clock from ENET_REF_CLK (same pin as ENET_TX_CLK on the chip) */ CGU_EntityConnect(CGU_CLKSRC_ENET_TX_CLK, CGU_BASE_PHY_RX); #else /* MII mode gets PHY RX clock from ENET_RX_CLK */ CGU_EntityConnect(CGU_CLKSRC_ENET_RX_CLK, CGU_BASE_PHY_RX); #endif /* Reset ethernet via RGU. This should be 1 clock, but we wait anyways. If the while loop really stalls, something else is wrong. */ LPC_RGU->RESET_CTRL0 = (1 << 22); timeout = 10; while (!(LPC_RGU->RESET_ACTIVE_STATUS0 & (1 << 22))) { msDelay(1); timeout--; if (timeout == 0) return ERR_TIMEOUT; } /* Reset MAC Subsystem internal registers and logic */ LPC_ETHERNET->DMA_BUS_MODE |= DMA_BM_SWR; timeout = 3; while (LPC_ETHERNET->DMA_BUS_MODE & DMA_BM_SWR) { msDelay(1); timeout--; if (timeout == 0) return ERR_TIMEOUT; } LPC_ETHERNET->DMA_BUS_MODE = DMA_BM_ATDS | DMA_BM_PBL(1) | DMA_BM_RPBL(1); /* Save MAC address */ LPC_ETHERNET->MAC_ADDR0_LOW = ((u32_t) netif->hwaddr[3] << 24) | ((u32_t) netif->hwaddr[2] << 16) | ((u32_t) netif->hwaddr[1] << 8) | (u32_t) netif->hwaddr[0]; LPC_ETHERNET->MAC_ADDR0_HIGH = ((u32_t) netif->hwaddr[5] << 8) | (u32_t) netif->hwaddr[4]; /* Initial MAC configuration for checksum offload, full duplex, 100Mbps, disable receive own in half duplex, inter-frame gap of 64-bits */ LPC_ETHERNET->MAC_CONFIG = MAC_CFG_BL(0) | MAC_CFG_IPC | MAC_CFG_DM | MAC_CFG_DO | MAC_CFG_FES | MAC_CFG_PS | MAC_CFG_IFG(3); /* Setup filter */ #if IP_SOF_BROADCAST_RECV LPC_ETHERNET->MAC_FRAME_FILTER = MAC_FF_PR | MAC_FF_RA; #else LPC_ETHERNET->MAC_FRAME_FILTER = 0; /* Only matching MAC address */ #endif /* Initialize the PHY */ err = lpc_phy_init(netif, LPC_EMAC_RMII); if (err != ERR_OK) return err; /* Setup transmit and receive descriptors */ if (lpc_tx_setup(lpc_netifdata) != ERR_OK) return ERR_BUF; if (lpc_rx_setup(lpc_netifdata) != ERR_OK) return ERR_BUF; /* Flush transmit FIFO */ LPC_ETHERNET->DMA_OP_MODE = DMA_OM_FTF; /* Setup DMA to flush receive FIFOs at 32 bytes, service TX FIFOs at 64 bytes */ LPC_ETHERNET->DMA_OP_MODE |= DMA_OM_RTC(1) | DMA_OM_TTC(0); /* Clear all MAC interrupts */ LPC_ETHERNET->DMA_STAT = DMA_ST_ALL; /* Enable MAC interrupts */ LPC_ETHERNET->DMA_INT_EN = #if NO_SYS == 1 0; #else DMA_IE_TIE | DMA_IE_OVE | DMA_IE_UNE | DMA_IE_RIE | DMA_IE_NIE | DMA_IE_AIE | DMA_IE_TUE | DMA_IE_RUE; #endif /* Enable receive and transmit DMA processes */ LPC_ETHERNET->DMA_OP_MODE |= DMA_OM_ST | DMA_OM_SR; /* Enable packet reception */ LPC_ETHERNET->MAC_CONFIG |= MAC_CFG_RE | MAC_CFG_TE; /* Start receive polling */ LPC_ETHERNET->DMA_REC_POLL_DEMAND = 1; return ERR_OK; }