void dma_channel_reset(uint32_t dma, uint8_t channel) { /* Disable channel and reset config bits. */ DMA_CCR(dma, channel) = 0; /* Reset data transfer number. */ DMA_CNDTR(dma, channel) = 0; /* Reset peripheral address. */ DMA_CPAR(dma, channel) = 0; /* Reset memory address. */ DMA_CMAR(dma, channel) = 0; /* Reset interrupt flags. */ DMA_IFCR(dma) |= DMA_IFCR_CIF(channel); }
void dma_set_read_from_peripheral(u32 dma, u8 channel) { DMA_CCR(dma, channel) &= ~DMA_CCR_DIR; }
void dma_set_peripheral_address(uint32_t dma, uint8_t channel, uint32_t address) { if (!(DMA_CCR(dma, channel) & DMA_CCR_EN)) { DMA_CPAR(dma, channel) = (uint32_t) address; } }
void dma_enable_channel(uint32_t dma, uint8_t channel) { DMA_CCR(dma, channel) |= DMA_CCR_EN; }
void dma_disable_half_transfer_interrupt(uint32_t dma, uint8_t channel) { DMA_CCR(dma, channel) &= ~DMA_CCR_HTIE; }
void dma_set_read_from_memory(uint32_t dma, uint8_t channel) { DMA_CCR(dma, channel) |= DMA_CCR_DIR; }
void dma_enable_circular_mode(uint32_t dma, uint8_t channel) { DMA_CCR(dma, channel) |= DMA_CCR_CIRC; DMA_CCR(dma, channel) &= ~DMA_CCR_MEM2MEM; }
void dma_disable_memory_increment_mode(uint32_t dma, uint8_t channel) { DMA_CCR(dma, channel) &= ~DMA_CCR_MINC; }
void dma_enable_channel(u32 dma, u8 channel) { DMA_CCR(dma, channel) |= DMA_CCR_EN; }
void dma_disable_transfer_complete_interrupt(u32 dma, u8 channel) { DMA_CCR(dma, channel) &= ~DMA_CCR_TCIE; }
void dma_disable_half_transfer_interrupt(u32 dma, u8 channel) { DMA_CCR(dma, channel) &= ~DMA_CCR_HTIE; }
void dma_enable_half_transfer_interrupt(u32 dma, u8 channel) { DMA_CCR(dma, channel) |= DMA_CCR_HTIE; }
void dma_disable_transfer_error_interrupt(u32 dma, u8 channel) { DMA_CCR(dma, channel) &= ~DMA_CCR_TEIE; }
void dma_enable_transfer_error_interrupt(u32 dma, u8 channel) { DMA_CCR(dma, channel) |= DMA_CCR_TEIE; }
void dma_set_read_from_memory(u32 dma, u8 channel) { DMA_CCR(dma, channel) |= DMA_CCR_DIR; }
void dma_set_memory_size(uint32_t dma, uint8_t channel, uint32_t mem_size) { DMA_CCR(dma, channel) &= ~(DMA_CCR_MSIZE_MASK); DMA_CCR(dma, channel) |= mem_size; }
void dma_set_peripheral_size(uint32_t dma, uint8_t channel, uint32_t peripheral_size) { DMA_CCR(dma, channel) &= ~(DMA_CCR_PSIZE_MASK); DMA_CCR(dma, channel) |= peripheral_size; }
void dma_disable_channel(u32 dma, u8 channel) { DMA_CCR(dma, channel) &= ~DMA_CCR_EN; }
void dma_disable_peripheral_increment_mode(uint32_t dma, uint8_t channel) { DMA_CCR(dma, channel) &= ~DMA_CCR_PINC; }
void dma_set_peripheral_address(u32 dma, u8 channel, u32 address) { if (!(DMA_CCR(dma, channel) & DMA_CCR_EN)) DMA_CPAR(dma, channel) = (u32) address; }
void dma_set_read_from_peripheral(uint32_t dma, uint8_t channel) { DMA_CCR(dma, channel) &= ~DMA_CCR_DIR; }
void dma_set_memory_address(u32 dma, u8 channel, u32 address) { if (!(DMA_CCR(dma, channel) & DMA_CCR_EN)) DMA_CMAR(dma, channel) = (u32) address; }
void dma_disable_transfer_error_interrupt(uint32_t dma, uint8_t channel) { DMA_CCR(dma, channel) &= ~DMA_CCR_TEIE; }
static int __init mx1_camera_probe(struct platform_device *pdev) { struct mx1_camera_dev *pcdev; struct resource *res; struct pt_regs regs; struct clk *clk; void __iomem *base; unsigned int irq; int err = 0; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); irq = platform_get_irq(pdev, 0); if (!res || (int)irq <= 0) { err = -ENODEV; goto exit; } clk = clk_get(&pdev->dev, "csi_clk"); if (IS_ERR(clk)) { err = PTR_ERR(clk); goto exit; } pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL); if (!pcdev) { dev_err(&pdev->dev, "Could not allocate pcdev\n"); err = -ENOMEM; goto exit_put_clk; } pcdev->res = res; pcdev->clk = clk; pcdev->pdata = pdev->dev.platform_data; if (pcdev->pdata) pcdev->mclk = pcdev->pdata->mclk_10khz * 10000; if (!pcdev->mclk) { dev_warn(&pdev->dev, "mclk_10khz == 0! Please, fix your platform data. " "Using default 20MHz\n"); pcdev->mclk = 20000000; } INIT_LIST_HEAD(&pcdev->capture); spin_lock_init(&pcdev->lock); /* * Request the regions. */ if (!request_mem_region(res->start, resource_size(res), DRIVER_NAME)) { err = -EBUSY; goto exit_kfree; } base = ioremap(res->start, resource_size(res)); if (!base) { err = -ENOMEM; goto exit_release; } pcdev->irq = irq; pcdev->base = base; /* request dma */ pcdev->dma_chan = imx_dma_request_by_prio(DRIVER_NAME, DMA_PRIO_HIGH); if (pcdev->dma_chan < 0) { dev_err(&pdev->dev, "Can't request DMA for MX1 CSI\n"); err = -EBUSY; goto exit_iounmap; } dev_dbg(&pdev->dev, "got DMA channel %d\n", pcdev->dma_chan); imx_dma_setup_handlers(pcdev->dma_chan, mx1_camera_dma_irq, NULL, pcdev); imx_dma_config_channel(pcdev->dma_chan, IMX_DMA_TYPE_FIFO, IMX_DMA_MEMSIZE_32, DMA_REQ_CSI_R, 0); /* burst length : 16 words = 64 bytes */ imx_dma_config_burstlen(pcdev->dma_chan, 0); /* request irq */ err = claim_fiq(&fh); if (err) { dev_err(&pdev->dev, "Camera interrupt register failed \n"); goto exit_free_dma; } set_fiq_handler(&mx1_camera_sof_fiq_start, &mx1_camera_sof_fiq_end - &mx1_camera_sof_fiq_start); regs.ARM_r8 = DMA_BASE + DMA_DIMR; regs.ARM_r9 = DMA_BASE + DMA_CCR(pcdev->dma_chan); regs.ARM_r10 = (long)pcdev->base + CSICR1; regs.ARM_fp = (long)pcdev->base + CSISR; regs.ARM_sp = 1 << pcdev->dma_chan; set_fiq_regs(®s); mxc_set_irq_fiq(irq, 1); enable_fiq(irq); pcdev->soc_host.drv_name = DRIVER_NAME; pcdev->soc_host.ops = &mx1_soc_camera_host_ops; pcdev->soc_host.priv = pcdev; pcdev->soc_host.v4l2_dev.dev = &pdev->dev; pcdev->soc_host.nr = pdev->id; err = soc_camera_host_register(&pcdev->soc_host); if (err) goto exit_free_irq; dev_info(&pdev->dev, "MX1 Camera driver loaded\n"); return 0; exit_free_irq: disable_fiq(irq); mxc_set_irq_fiq(irq, 0); release_fiq(&fh); exit_free_dma: imx_dma_free(pcdev->dma_chan); exit_iounmap: iounmap(base); exit_release: release_mem_region(res->start, resource_size(res)); exit_kfree: kfree(pcdev); exit_put_clk: clk_put(clk); exit: return err; }
void dma_disable_transfer_complete_interrupt(uint32_t dma, uint8_t channel) { DMA_CCR(dma, channel) &= ~DMA_CCR_TCIE; }
void dma_enable_mem2mem_mode(uint32_t dma, uint8_t channel) { DMA_CCR(dma, channel) |= DMA_CCR_MEM2MEM; DMA_CCR(dma, channel) &= ~DMA_CCR_CIRC; }
void dma_disable_channel(uint32_t dma, uint8_t channel) { DMA_CCR(dma, channel) &= ~DMA_CCR_EN; }
void dma_set_priority(uint32_t dma, uint8_t channel, uint32_t prio) { DMA_CCR(dma, channel) &= ~(DMA_CCR_PL_MASK); DMA_CCR(dma, channel) |= prio; }
void dma_set_memory_address(uint32_t dma, uint8_t channel, uint32_t address) { if (!(DMA_CCR(dma, channel) & DMA_CCR_EN)) { DMA_CMAR(dma, channel) = (uint32_t) address; } }
void dma_enable_circular_mode(u32 dma, u8 channel) { DMA_CCR(dma, channel) |= DMA_CCR_CIRC; DMA_CCR(dma, channel) &= ~DMA_CCR_MEM2MEM; }