/* Initialize the Rx Transmit Control Discriptor parameters*/ static void rx_tcd_init(struct tdm_priv *priv) { int i; u32 iter; u32 offset; dma_addr_t physaddr; int bytes_in_fifo_per_frame = ALIGN_SIZE(priv->cfg.num_ch * priv->cfg.ch_width, 8); iter = bytes_in_fifo_per_frame / 8 * priv->cfg.num_frames; for (i = 0; i < NUM_OF_TDM_BUF; i++) { /* TDM RX fifo address */ priv->dma_rx_tcd[i]->tcd[0] = TDM_RDR_OFFSET + priv->ptdm_base; /* ssize=dsize=64bit, soff=smod=dmod=0 */ priv->dma_rx_tcd[i]->tcd[1] = DMA_TCD1_SSIZE(SSIZE_64BITS) | DMA_TCD1_DSIZE(SSIZE_64BITS); /* number of bytes for minor loop, wide fifo 8bytes for dma */ priv->dma_rx_tcd[i]->tcd[2] = 8; /* slast = 0 */ priv->dma_rx_tcd[i]->tcd[3] = 0; offset = i * priv->cfg.num_frames * bytes_in_fifo_per_frame; /* dadr = rx buffer address */ priv->dma_rx_tcd[i]->tcd[4] = priv->dma_input_paddr + offset; /* channel to channel linking is disabled , * destination offset is inc destination adr by 8, * current iteration(citer) = number of transfers for frame */ priv->dma_rx_tcd[i]->tcd[5] = DMA_TCD5_DOFF(0x08) | DMA_TCD5_CITER_DISABLE_LINK(iter); /* enable scater gather, interrupt on 1 Frame, */ priv->dma_rx_tcd[i]->tcd[7] = DMA_TCD7_BITER_DISABLE_LINK(iter) | DMA_TCD7_E_SG | DMA_TCD7_INT_MAJ; priv->dma_rx_tcd[i]->tcd[6] = 0; } /* Next TCD for SG operation */ physaddr = priv->dma_rx_tcd_paddr; priv->dma_rx_tcd[2]->tcd[6] = ALIGN_SIZE(physaddr, ALIGNED_32_BYTES); physaddr += TCD_BUFFER_SIZE; priv->dma_rx_tcd[0]->tcd[6] = ALIGN_SIZE(physaddr, ALIGNED_32_BYTES); physaddr += TCD_BUFFER_SIZE; priv->dma_rx_tcd[1]->tcd[6] = ALIGN_SIZE(physaddr, ALIGNED_32_BYTES); }
/* Initialize the Rx Transmit Control Discriptor parameters*/ static void rx_tcd_init(struct tdm_priv *priv) { int i; u32 iter; u32 offset; dma_addr_t physaddr; struct tdm_adapter *adap; int bytes_in_fifo_per_frame; adap = priv->adap; if (!adap) { pr_err("%s: Invalid handle\n", __func__); return; } bytes_in_fifo_per_frame = ALIGN_SIZE(adap->adapt_cfg.num_ch * adap->adapt_cfg.slot_width, 8); iter = (bytes_in_fifo_per_frame / NBYTES) * adap->adapt_cfg.num_frames; for (i = 0; i < NUM_OF_TDM_BUF; i++) { /* TDM RX fifo address */ priv->dma_rx_tcd[i]->tcd[0] = TDM_RDR_OFFSET + priv->ptdm_base; /* ssize=dsize=64bit, soff=smod=dmod=0 */ priv->dma_rx_tcd[i]->tcd[1] = DMA_TCD1_SSIZE(SSIZE_64BITS) | DMA_TCD1_DSIZE(SSIZE_64BITS); /* number of bytes for minor loop, wide fifo 8bytes for dma */ priv->dma_rx_tcd[i]->tcd[2] = NBYTES; /* slast = 0 */ priv->dma_rx_tcd[i]->tcd[3] = SLAST; offset = i * adap->adapt_cfg.num_frames * bytes_in_fifo_per_frame; /* dadr = rx buffer address */ priv->dma_rx_tcd[i]->tcd[4] = (u32)priv->dma_input_paddr + offset; /* channel to channel linking is disabled , * destination offset is inc destination adr by 8, * current iteration(citer) = number of transfers for frame */ priv->dma_rx_tcd[i]->tcd[5] = DMA_TCD5_DOFF(DOFF_VAL) | DMA_TCD5_CITER_DISABLE_LINK(iter); /* enable scater gather, interrupt on 1 Frame, */ priv->dma_rx_tcd[i]->tcd[7] = DMA_TCD7_BITER_DISABLE_LINK(iter) | DMA_TCD7_E_SG | DMA_TCD7_INT_MAJ; priv->dma_rx_tcd[i]->tcd[6] = DLAST_SGA; } /* Next TCD for SG operation */ physaddr = priv->dma_rx_tcd_paddr; priv->dma_rx_tcd[2]->tcd[6] = ALIGN_SIZE(physaddr, ALIGNED_32_BYTES); physaddr += TCD_BUFFER_SIZE; priv->dma_rx_tcd[0]->tcd[6] = ALIGN_SIZE(physaddr, ALIGNED_32_BYTES); physaddr += TCD_BUFFER_SIZE; priv->dma_rx_tcd[1]->tcd[6] = ALIGN_SIZE(physaddr, ALIGNED_32_BYTES); }