예제 #1
0
void rtl8225z2_SetTXPowerLevel(struct net_device *dev, short ch)
{
	struct r8180_priv *priv = ieee80211_priv(dev);
	u8 max_cck_power_level;
	u8 max_ofdm_power_level;
	u8 min_ofdm_power_level;
	char cck_power_level = (char)(0xff & priv->chtxpwr[ch]);
	char ofdm_power_level = (char)(0xff & priv->chtxpwr_ofdm[ch]);

	if (IS_DOT11D_ENABLE(priv->ieee80211) &&
	    IS_DOT11D_STATE_DONE(priv->ieee80211)) {
		u8 MaxTxPwrInDbm = DOT11D_GetMaxTxPwrInDbm(priv->ieee80211, ch);
		u8 CckMaxPwrIdx = DbmToTxPwrIdx(priv, WIRELESS_MODE_B,
							MaxTxPwrInDbm);
		u8 OfdmMaxPwrIdx = DbmToTxPwrIdx(priv, WIRELESS_MODE_G,
							MaxTxPwrInDbm);

		if (cck_power_level > CckMaxPwrIdx)
			cck_power_level = CckMaxPwrIdx;
		if (ofdm_power_level > OfdmMaxPwrIdx)
			ofdm_power_level = OfdmMaxPwrIdx;
	}

	max_cck_power_level = 15;
	max_ofdm_power_level = 25;
	min_ofdm_power_level = 10;

	if (cck_power_level > 35)
		cck_power_level = 35;

	write_nic_byte(dev, CCK_TXAGC,
		       (ZEBRA2_CCK_OFDM_GAIN_SETTING[(u8)cck_power_level]));
	force_pci_posting(dev);
	mdelay(1);

	if (ofdm_power_level > 35)
		ofdm_power_level = 35;

	if (priv->up == 0) {
		write_phy_ofdm(dev, 2, 0x42);
		write_phy_ofdm(dev, 5, 0x00);
		write_phy_ofdm(dev, 6, 0x40);
		write_phy_ofdm(dev, 7, 0x00);
		write_phy_ofdm(dev, 8, 0x40);
	}

	write_nic_byte(dev, OFDM_TXAGC,
		       ZEBRA2_CCK_OFDM_GAIN_SETTING[(u8)ofdm_power_level]);

	if (ofdm_power_level <= 11) {
		write_phy_ofdm(dev, 0x07, 0x5c);
		write_phy_ofdm(dev, 0x09, 0x5c);
	}

	if (ofdm_power_level <= 17) {
		write_phy_ofdm(dev, 0x07, 0x54);
		write_phy_ofdm(dev, 0x09, 0x54);
	} else {
		write_phy_ofdm(dev, 0x07, 0x50);
		write_phy_ofdm(dev, 0x09, 0x50);
	}

	force_pci_posting(dev);
	mdelay(1);
}
예제 #2
0
void rtl8225z2_SetTXPowerLevel(struct net_device *dev, short ch)
{
	struct r8180_priv *priv = ieee80211_priv(dev);

//	int GainIdx;
//	int GainSetting;
	//int i;
	//u8 power;
	//u8 *cck_power_table;
	u8 max_cck_power_level;
	//u8 min_cck_power_level;
	u8 max_ofdm_power_level;
	u8 min_ofdm_power_level;
//	u8 cck_power_level = 0xff & priv->chtxpwr[ch];//-by amy 080312
//	u8 ofdm_power_level = 0xff & priv->chtxpwr_ofdm[ch];//-by amy 080312
	char cck_power_level = (char)(0xff & priv->chtxpwr[ch]);//+by amy 080312
	char ofdm_power_level = (char)(0xff & priv->chtxpwr_ofdm[ch]);//+by amy 080312
#if 0
	//
	// CCX 2 S31, AP control of client transmit power:
	// 1. We shall not exceed Cell Power Limit as possible as we can.
	// 2. Tolerance is +/- 5dB.
	// 3. 802.11h Power Contraint takes higher precedence over CCX Cell Power Limit.
	//
	// TODO:
	// 1. 802.11h power contraint
	//
	// 071011, by rcnjko.
	//
	if(	priv->OpMode == RT_OP_MODE_INFRASTRUCTURE &&
		priv->bWithCcxCellPwr &&
		ch == priv->dot11CurrentChannelNumber)
	{
		u8 CckCellPwrIdx = DbmToTxPwrIdx(dev, WIRELESS_MODE_B, pMgntInfo->CcxCellPwr);
		u8 OfdmCellPwrIdx = DbmToTxPwrIdx(dev, WIRELESS_MODE_G, pMgntInfo->CcxCellPwr);

		printk("CCX Cell Limit: %d dBm => CCK Tx power index : %d, OFDM Tx power index: %d\n",
			priv->CcxCellPwr, CckCellPwrIdx, OfdmCellPwrIdx);
		printk("EEPROM channel(%d) => CCK Tx power index: %d, OFDM Tx power index: %d\n",
			channel, CckTxPwrIdx, OfdmTxPwrIdx);

		if(cck_power_level > CckCellPwrIdx)
			cck_power_level = CckCellPwrIdx;
		if(ofdm_power_level > OfdmCellPwrIdx)
			ofdm_power_level = OfdmCellPwrIdx;

		printk("Altered CCK Tx power index : %d, OFDM Tx power index: %d\n",
			CckTxPwrIdx, OfdmTxPwrIdx);
	}
#endif
#ifdef ENABLE_DOT11D
	if(IS_DOT11D_ENABLE(priv->ieee80211) &&
		IS_DOT11D_STATE_DONE(priv->ieee80211) )
	{
		//PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(priv->ieee80211);
		u8 MaxTxPwrInDbm = DOT11D_GetMaxTxPwrInDbm(priv->ieee80211, ch);
		u8 CckMaxPwrIdx = DbmToTxPwrIdx(priv, WIRELESS_MODE_B, MaxTxPwrInDbm);
		u8 OfdmMaxPwrIdx = DbmToTxPwrIdx(priv, WIRELESS_MODE_G, MaxTxPwrInDbm);

		//printk("Max Tx Power dBm (%d) => CCK Tx power index : %d, OFDM Tx power index: %d\n", MaxTxPwrInDbm, CckMaxPwrIdx, OfdmMaxPwrIdx);

		//printk("EEPROM channel(%d) => CCK Tx power index: %d, OFDM Tx power index: %d\n",
		//	ch, cck_power_level, ofdm_power_level);

		if(cck_power_level > CckMaxPwrIdx)
			cck_power_level = CckMaxPwrIdx;
		if(ofdm_power_level > OfdmMaxPwrIdx)
			ofdm_power_level = OfdmMaxPwrIdx;
	}

	//priv->CurrentCckTxPwrIdx = cck_power_level;
	//priv->CurrentOfdmTxPwrIdx = ofdm_power_level;
#endif

	max_cck_power_level = 15;
	max_ofdm_power_level = 25; //  12 -> 25
	min_ofdm_power_level = 10;

#ifdef CONFIG_RTL8185B
#ifdef CONFIG_RTL818X_S

	if(cck_power_level > 35)
	{
		cck_power_level = 35;
	}
	//
	// Set up CCK TXAGC. suggested by SD3 SY.
	//
       write_nic_byte(dev, CCK_TXAGC, (ZEBRA2_CCK_OFDM_GAIN_SETTING[(u8)cck_power_level]) );
       //printk("CCK TX power is %x\n", (ZEBRA2_CCK_OFDM_GAIN_SETTING[cck_power_level]));
       force_pci_posting(dev);
	mdelay(1);
#else

	/* CCK power setting */
	if(cck_power_level > max_cck_power_level)
		cck_power_level = max_cck_power_level;

	cck_power_level += priv->cck_txpwr_base;

	if(cck_power_level > 35)
		cck_power_level = 35;

	if(ch == 14)
		cck_power_table = rtl8225z2_tx_power_cck_ch14;
	else
		cck_power_table = rtl8225z2_tx_power_cck;


	for(i=0;i<8;i++){

		power = cck_power_table[i];
		write_phy_cck(dev, 0x44 + i, power);
	}

	//write_nic_byte(dev, TX_GAIN_CCK, power);
	//2005.11.17,
	write_nic_byte(dev, CCK_TXAGC, ZEBRA2_CCK_OFDM_GAIN_SETTING[(u8)cck_power_level]);

	force_pci_posting(dev);
	mdelay(1);
#endif
#endif
	/* OFDM power setting */
//  Old:
//	if(ofdm_power_level > max_ofdm_power_level)
//		ofdm_power_level = 35;
//	ofdm_power_level += min_ofdm_power_level;
//  Latest:
/*	if(ofdm_power_level > (max_ofdm_power_level - min_ofdm_power_level))
		ofdm_power_level = max_ofdm_power_level;
	else
		ofdm_power_level += min_ofdm_power_level;

	ofdm_power_level += priv->ofdm_txpwr_base;
*/
	if(ofdm_power_level > 35)
		ofdm_power_level = 35;

//	rtl8185_set_anaparam2(dev,RTL8225_ANAPARAM2_ON);

	//rtl8185_set_anaparam2(dev, ANAPARM2_ASIC_ON);

	if (priv->up == 0) {
		//must add these for rtl8185B down, xiong-2006-11-21
		write_phy_ofdm(dev,2,0x42);
		write_phy_ofdm(dev,5,0);
		write_phy_ofdm(dev,6,0x40);
		write_phy_ofdm(dev,7,0);
		write_phy_ofdm(dev,8,0x40);
	}

	//write_nic_byte(dev, TX_GAIN_OFDM, ofdm_power_level);
	//2005.11.17,
#ifdef CONFIG_RTL818X_S
        write_nic_byte(dev, OFDM_TXAGC, ZEBRA2_CCK_OFDM_GAIN_SETTING[(u8)ofdm_power_level]);
#else
        write_nic_byte(dev, OFDM_TXAGC, ZEBRA2_CCK_OFDM_GAIN_SETTING[(u8)ofdm_power_level]*2);
#endif
        if(ofdm_power_level<=11)
        {
//            write_nic_dword(dev,PHY_ADR,0x00005c87);
//            write_nic_dword(dev,PHY_ADR,0x00005c89);
		write_phy_ofdm(dev,0x07,0x5c);
		write_phy_ofdm(dev,0x09,0x5c);
        }
	if(ofdm_power_level<=17)
        {
//             write_nic_dword(dev,PHY_ADR,0x00005487);
//             write_nic_dword(dev,PHY_ADR,0x00005489);
		write_phy_ofdm(dev,0x07,0x54);
		write_phy_ofdm(dev,0x09,0x54);
        }
        else
        {
//             write_nic_dword(dev,PHY_ADR,0x00005087);
//             write_nic_dword(dev,PHY_ADR,0x00005089);
		write_phy_ofdm(dev,0x07,0x50);
		write_phy_ofdm(dev,0x09,0x50);
        }
	force_pci_posting(dev);
	mdelay(1);

}