static int rk32_edp_process_clock_recovery(struct rk32_edp *edp) { u8 link_status[2]; int lane; int lane_count; u8 adjust_request[2]; u8 voltage_swing; u8 pre_emphasis; u8 training_lane; int retval; udelay(100); lane_count = edp->link_train.lane_count; retval = rk32_edp_read_bytes_from_dpcd(edp, DPCD_LANE0_1_STATUS, 2, link_status); if (retval < 0) { dev_err(edp->dev, "failed to read lane status!\n"); return retval; } if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) { /* set training pattern 2 for EQ */ rk32_edp_set_training_pattern(edp, TRAINING_PTN2); for (lane = 0; lane < lane_count; lane++) { retval = rk32_edp_read_bytes_from_dpcd(edp, DPCD_ADJUST_REQUEST_LANE0_1, 2, adjust_request); if (retval < 0) { dev_err(edp->dev, "failed to read adjust request!\n"); return retval; } voltage_swing = rk32_edp_get_adjust_request_voltage( adjust_request, lane); pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis( adjust_request, lane); training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | DPCD_PRE_EMPHASIS_SET(pre_emphasis); if (voltage_swing == VOLTAGE_LEVEL_3) training_lane |= DPCD_MAX_SWING_REACHED; if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED; edp->link_train.training_lane[lane] = training_lane; rk32_edp_set_lane_link_training(edp, edp->link_train.training_lane[lane], lane); } retval = rk32_edp_write_byte_to_dpcd(edp, DPCD_TRAINING_PATTERN_SET, DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_2); if (retval < 0) { dev_err(edp->dev, "failed to set training pattern 2!\n"); return retval; } retval = rk32_edp_write_bytes_to_dpcd(edp, DPCD_TRAINING_LANE0_SET, lane_count, edp->link_train.training_lane); if (retval < 0) { dev_err(edp->dev, "failed to set training lane!\n"); return retval; } dev_info(edp->dev, "Link Training Clock Recovery success\n"); edp->link_train.lt_state = LT_EQ_TRAINING; } else { for (lane = 0; lane < lane_count; lane++) { training_lane = rk32_edp_get_lane_link_training( edp, lane); retval = rk32_edp_read_bytes_from_dpcd(edp, DPCD_ADJUST_REQUEST_LANE0_1, 2, adjust_request); if (retval < 0) { dev_err(edp->dev, "failed to read adjust request!\n"); return retval; } voltage_swing = rk32_edp_get_adjust_request_voltage( adjust_request, lane); pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis( adjust_request, lane); if (voltage_swing == VOLTAGE_LEVEL_3 || pre_emphasis == PRE_EMPHASIS_LEVEL_3) { dev_err(edp->dev, "voltage or pre emphasis reached max level\n"); goto reduce_link_rate; } if ((DPCD_VOLTAGE_SWING_GET(training_lane) == voltage_swing) && (DPCD_PRE_EMPHASIS_GET(training_lane) == pre_emphasis)) { edp->link_train.cr_loop[lane]++; if (edp->link_train.cr_loop[lane] == MAX_CR_LOOP) { dev_err(edp->dev, "CR Max loop\n"); goto reduce_link_rate; } } training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | DPCD_PRE_EMPHASIS_SET(pre_emphasis); if (voltage_swing == VOLTAGE_LEVEL_3) training_lane |= DPCD_MAX_SWING_REACHED; if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED; edp->link_train.training_lane[lane] = training_lane; rk32_edp_set_lane_link_training(edp, edp->link_train.training_lane[lane], lane); } retval = rk32_edp_write_bytes_to_dpcd(edp, DPCD_TRAINING_LANE0_SET, lane_count, edp->link_train.training_lane); if (retval < 0) { dev_err(edp->dev, "failed to set training lane!\n"); return retval; } } return 0; reduce_link_rate: rk32_edp_reduce_link_rate(edp); return -EIO; }
static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp) { u8 data; u8 link_status[6]; int lane; int lane_count; u8 buf[5]; u8 *adjust_request; u8 voltage_swing; u8 pre_emphasis; u8 training_lane; udelay(100); exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS, 6, link_status); lane_count = dp->link_train.lane_count; if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) { /* set training pattern 2 for EQ */ exynos_dp_set_training_pattern(dp, TRAINING_PTN2); adjust_request = link_status + (DPCD_ADDR_ADJUST_REQUEST_LANE0_1 - DPCD_ADDR_LANE0_1_STATUS); exynos_dp_get_adjust_train(dp, adjust_request); buf[0] = DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_2; exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_TRAINING_LANE0_SET, buf[0]); for (lane = 0; lane < lane_count; lane++) { exynos_dp_set_lane_link_training(dp, dp->link_train.training_lane[lane], lane); buf[lane] = dp->link_train.training_lane[lane]; exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_TRAINING_LANE0_SET + lane, buf[lane]); } dp->link_train.lt_state = EQUALIZER_TRAINING; } else { exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_ADJUST_REQUEST_LANE0_1, &data); adjust_request[0] = data; exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_ADJUST_REQUEST_LANE2_3, &data); adjust_request[1] = data; for (lane = 0; lane < lane_count; lane++) { training_lane = exynos_dp_get_lane_link_training( dp, lane); voltage_swing = exynos_dp_get_adjust_request_voltage( adjust_request, lane); pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis( adjust_request, lane); if ((DPCD_VOLTAGE_SWING_GET(training_lane) == voltage_swing) && (DPCD_PRE_EMPHASIS_GET(training_lane) == pre_emphasis)) dp->link_train.cr_loop[lane]++; dp->link_train.training_lane[lane] = training_lane; } if (exynos_dp_check_max_cr_loop(dp, voltage_swing) != 0) { exynos_dp_reduce_link_rate(dp); } else { exynos_dp_get_adjust_train(dp, adjust_request); for (lane = 0; lane < lane_count; lane++) { exynos_dp_set_lane_link_training(dp, dp->link_train.training_lane[lane], lane); buf[lane] = dp->link_train.training_lane[lane]; exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_TRAINING_LANE0_SET + lane, buf[lane]); } } } return 0; }
static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp) { int lane, lane_count, retval; u8 voltage_swing, pre_emphasis, training_lane; u8 link_status[2], adjust_request[2]; usleep_range(100, 101); lane_count = dp->link_train.lane_count; retval = exynos_dp_read_bytes_from_dpcd(dp, DP_LANE0_1_STATUS, 2, link_status); if (retval) return retval; retval = exynos_dp_read_bytes_from_dpcd(dp, DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); if (retval) return retval; if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) { /* set training pattern 2 for EQ */ exynos_dp_set_training_pattern(dp, TRAINING_PTN2); retval = exynos_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET, DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2); if (retval) return retval; dev_info(dp->dev, "Link Training Clock Recovery success\n"); dp->link_train.lt_state = EQUALIZER_TRAINING; } else { for (lane = 0; lane < lane_count; lane++) { training_lane = exynos_dp_get_lane_link_training( dp, lane); voltage_swing = exynos_dp_get_adjust_request_voltage( adjust_request, lane); pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis( adjust_request, lane); if (DPCD_VOLTAGE_SWING_GET(training_lane) == voltage_swing && DPCD_PRE_EMPHASIS_GET(training_lane) == pre_emphasis) dp->link_train.cr_loop[lane]++; if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP || voltage_swing == VOLTAGE_LEVEL_3 || pre_emphasis == PRE_EMPHASIS_LEVEL_3) { dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n", dp->link_train.cr_loop[lane], voltage_swing, pre_emphasis); exynos_dp_reduce_link_rate(dp); return -EIO; } } } exynos_dp_get_adjust_training_lane(dp, adjust_request); for (lane = 0; lane < lane_count; lane++) exynos_dp_set_lane_link_training(dp, dp->link_train.training_lane[lane], lane); retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, lane_count, dp->link_train.training_lane); if (retval) return retval; return retval; }
static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp) { u8 link_status[2]; int lane; int lane_count; u8 adjust_request[2]; u8 voltage_swing; u8 pre_emphasis; u8 training_lane; usleep_range(100, 101); lane_count = dp->link_train.lane_count; exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS, 2, link_status); if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) { /* set training pattern 2 for EQ */ exynos_dp_set_training_pattern(dp, TRAINING_PTN2); for (lane = 0; lane < lane_count; lane++) { exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_ADJUST_REQUEST_LANE0_1, 2, adjust_request); voltage_swing = exynos_dp_get_adjust_request_voltage( adjust_request, lane); pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis( adjust_request, lane); training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | DPCD_PRE_EMPHASIS_SET(pre_emphasis); if (voltage_swing == VOLTAGE_LEVEL_3) training_lane |= DPCD_MAX_SWING_REACHED; if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED; dp->link_train.training_lane[lane] = training_lane; exynos_dp_set_lane_link_training(dp, dp->link_train.training_lane[lane], lane); } exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_TRAINING_PATTERN_SET, DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_2); exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_TRAINING_LANE0_SET, lane_count, dp->link_train.training_lane); dev_info(dp->dev, "Link Training Clock Recovery success\n"); dp->link_train.lt_state = EQUALIZER_TRAINING; } else { for (lane = 0; lane < lane_count; lane++) { training_lane = exynos_dp_get_lane_link_training( dp, lane); exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_ADJUST_REQUEST_LANE0_1, 2, adjust_request); voltage_swing = exynos_dp_get_adjust_request_voltage( adjust_request, lane); pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis( adjust_request, lane); if (voltage_swing == VOLTAGE_LEVEL_3 || pre_emphasis == PRE_EMPHASIS_LEVEL_3) { dev_err(dp->dev, "voltage or pre emphasis reached max level\n"); goto reduce_link_rate; } if ((DPCD_VOLTAGE_SWING_GET(training_lane) == voltage_swing) && (DPCD_PRE_EMPHASIS_GET(training_lane) == pre_emphasis)) { dp->link_train.cr_loop[lane]++; if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP) { dev_err(dp->dev, "CR Max loop\n"); goto reduce_link_rate; } } training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | DPCD_PRE_EMPHASIS_SET(pre_emphasis); if (voltage_swing == VOLTAGE_LEVEL_3) training_lane |= DPCD_MAX_SWING_REACHED; if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED; dp->link_train.training_lane[lane] = training_lane; exynos_dp_set_lane_link_training(dp, dp->link_train.training_lane[lane], lane); } exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_TRAINING_LANE0_SET, lane_count, dp->link_train.training_lane); } return 0; reduce_link_rate: exynos_dp_reduce_link_rate(dp); return -EIO; }