{ 0x0b0011, 1030},
{ 0x0a0012, 1040},
{ 0x090013, 1050},
{ 0x080014, 1060},
{ 0x070015, 1070},
{ 0x060016, 1080},
{ 0x050017, 1090},
{ 0x040018, 1100},
{ 0x030019, 1110},
{ 0x02001a, 1120},
{ 0x01001b, 1130},
{ 0x00001c, 1140}
};
struct scpi_opp_entry cpu_dvfs_tbl[] = {
DVFS( 100000000, 860),
DVFS( 250000000, 860),
DVFS( 500000000, 860),
DVFS( 667000000, 900),
DVFS(1000000000, 940),
DVFS(1200000000, 1020),
DVFS(1416000000, 1110),
DVFS(1536000000, 1110),
DVFS(1752000000, 1110),
DVFS(2016000000, 1110)
};
struct scpi_opp_entry vlittle_dvfs_tbl[] = {
DVFS( 100000000, 860),
DVFS( 250000000, 860),
DVFS( 500000000, 860),
DVFS( 667000000, 900),
{ 0x0b0011, 1030},
{ 0x0a0012, 1040},
{ 0x090013, 1050},
{ 0x080014, 1060},
{ 0x070015, 1070},
{ 0x060016, 1080},
{ 0x050017, 1090},
{ 0x040018, 1100},
{ 0x030019, 1110},
{ 0x02001a, 1120},
{ 0x01001b, 1130},
{ 0x00001c, 1140}
};
struct scpi_opp_entry cpu_dvfs_tbl[] = {
DVFS( 100000000, 860),
DVFS( 250000000, 860),
DVFS( 500000000, 880),
DVFS( 667000000, 920),
DVFS(1000000000, 960),
DVFS(1200000000, 1040),
DVFS(1296000000, 1080),
DVFS(1416000000, 1110),
DVFS(1536000000, 1110),
DVFS(1752000000, 1110),
DVFS(2016000000, 1110)
};
#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
{ 0x090013, 1050},
{ 0x080014, 1060},
{ 0x070015, 1070},
{ 0x060016, 1080},
{ 0x050017, 1090},
{ 0x040018, 1100},
{ 0x030019, 1110},
{ 0x02001a, 1120},
{ 0x01001b, 1130},
{ 0x00001c, 1140}
};
#define CHIP_ADJUST 20
#define RIPPLE_ADJUST 30
struct scpi_opp_entry cpu_dvfs_tbl[] = {
DVFS( 100000000, 860+CHIP_ADJUST+RIPPLE_ADJUST),
DVFS( 250000000, 860+CHIP_ADJUST+RIPPLE_ADJUST),
DVFS( 500000000, 860+CHIP_ADJUST+RIPPLE_ADJUST),
DVFS( 667000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
DVFS(1000000000, 940+CHIP_ADJUST+RIPPLE_ADJUST),
DVFS(1200000000, 980+CHIP_ADJUST+RIPPLE_ADJUST),
DVFS(1296000000, 1000+CHIP_ADJUST+RIPPLE_ADJUST),
DVFS(1416000000, 1020+CHIP_ADJUST+RIPPLE_ADJUST),
DVFS(1536000000, 1050+CHIP_ADJUST+RIPPLE_ADJUST),
DVFS(1800000000, 1050+CHIP_ADJUST+RIPPLE_ADJUST),
};
#define P_PIN_MUX_REG10 (*((volatile unsigned *)(0xc8834400 + ( 0x36 << 2))))
#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
{ 0x0b0011, 1030},
{ 0x0a0012, 1040},
{ 0x090013, 1050},
{ 0x080014, 1060},
{ 0x070015, 1070},
{ 0x060016, 1080},
{ 0x050017, 1090},
{ 0x040018, 1100},
{ 0x030019, 1110},
{ 0x02001a, 1120},
{ 0x01001b, 1130},
{ 0x00001c, 1140}
};
struct scpi_opp_entry cpu_dvfs_tbl[] = {
DVFS( 100000000, 860+50),
DVFS( 250000000, 860+50),
DVFS( 500000000, 860+50),
DVFS( 667000000, 900+50),
DVFS(1000000000, 940+50),
DVFS(1200000000, 980+50),
DVFS(1296000000, 1000+50),
DVFS(1416000000, 1020+50),
DVFS(1536000000, 1050+50),
DVFS(1800000000, 1050+50),
};
#define P_PIN_MUX_REG10 (*((volatile unsigned *)(0xc8834400 + ( 0x36 << 2))))
#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
#include "pwm_ctrl.h"
#define CHIP_ADJUST 20
#define RIPPLE_ADJUST 30
struct scpi_opp_entry cpu_dvfs_tbl[] = {
DVFS( 100000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
DVFS( 250000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
DVFS( 500000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
DVFS( 667000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
DVFS(1000000000, 910+CHIP_ADJUST+RIPPLE_ADJUST),
DVFS(1200000000, 970+CHIP_ADJUST+RIPPLE_ADJUST),
DVFS(1296000000, 1010+CHIP_ADJUST+RIPPLE_ADJUST),
DVFS(1416000000, 1080+CHIP_ADJUST+RIPPLE_ADJUST),
};
#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
#define P_PIN_MUX_REG4 (*((volatile unsigned *)(0xda834400 + (0x30 << 2))))
#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
