__s32 BSP_disp_lcd_open_before(__u32 sel)
{
disp_clk_cfg(sel, DISP_OUTPUT_TYPE_LCD, DIS_NULL);
lcdc_clk_on(sel);
image_clk_on(sel);
/*
* set image normal channel start bit, because every de_clk_off( )
* will reset this bit
*/
Image_open(sel);
Disp_lcdc_pin_cfg(sel, DISP_OUTPUT_TYPE_LCD, 1);
if (gpanel_info[sel].tcon_index == 0)
TCON0_cfg(sel, (__panel_para_t *) &gpanel_info[sel]);
else
TCON1_cfg_ex(sel, (__panel_para_t *) &gpanel_info[sel]);
#ifdef CONFIG_ARCH_SUN4I
BSP_disp_set_output_csc(sel, DISP_OUTPUT_TYPE_LCD);
#else
BSP_disp_set_output_csc(sel, DISP_OUTPUT_TYPE_LCD,
gdisp.screen[sel].iep_status & DRC_USED);
#endif
DE_BE_set_display_size(sel, gpanel_info[sel].lcd_x,
gpanel_info[sel].lcd_y);
DE_BE_Output_Select(sel, sel);
open_flow[sel].func_num = 0;
lcd_panel_fun[sel].cfg_open_flow(sel);
return DIS_SUCCESS;
}
__s32 BSP_disp_lcd_open_before(__u32 sel)
{
disp_clk_cfg(sel, DISP_OUTPUT_TYPE_LCD, DIS_NULL);
lcdc_clk_on(sel);
image_clk_on(sel);
Image_open(sel);//set image normal channel start bit , because every de_clk_off( )will reset this bit
Disp_lcdc_pin_cfg(sel, DISP_OUTPUT_TYPE_LCD, 1);
if(gpanel_info[sel].tcon_index == 0)
{
TCON0_cfg(sel,(__panel_para_t*)&gpanel_info[sel]);
}
else
{
TCON1_cfg_ex(sel,(__panel_para_t*)&gpanel_info[sel]);
}
BSP_disp_set_output_csc(sel, DISP_OUTPUT_TYPE_LCD);
DE_BE_set_display_size(sel, gpanel_info[sel].lcd_x, gpanel_info[sel].lcd_y);
DE_BE_Output_Select(sel, sel);
open_flow[sel].func_num = 0;
lcd_panel_fun[sel].cfg_open_flow(sel);
return DIS_SUCCESS;
}
__s32 BSP_disp_lcd_close_befor(__u32 sel)
{
close_flow[sel].func_num = 0;
lcd_panel_fun[sel].cfg_close_flow(sel);
Disp_lcdc_pin_cfg(sel, DISP_OUTPUT_TYPE_LCD, 0);
return DIS_SUCCESS;
}
__s32 BSP_disp_vga_open(__u32 sel)
{
if (!(gdisp.screen[sel].status & VGA_ON)) {
__disp_vga_mode_t vga_mode;
__u32 i = 0;
vga_mode = gdisp.screen[sel].vga_mode;
lcdc_clk_on(sel);
image_clk_on(sel);
/*
* set image normal channel start bit , because every
* de_clk_off( ) will reset this bit
*/
Image_open(sel);
tve_clk_on(sel);
disp_clk_cfg(sel, DISP_OUTPUT_TYPE_VGA, vga_mode);
Disp_lcdc_pin_cfg(sel, DISP_OUTPUT_TYPE_VGA, 1);
#ifdef CONFIG_ARCH_SUN4I
BSP_disp_set_output_csc(sel, DISP_OUTPUT_TYPE_VGA);
#else
BSP_disp_set_output_csc(sel, DISP_OUTPUT_TYPE_VGA,
gdisp.screen[sel].
iep_status & DRC_USED);
#endif
DE_BE_set_display_size(sel, vga_mode_to_width(vga_mode),
vga_mode_to_height(vga_mode));
DE_BE_Output_Select(sel, sel);
TCON1_set_vga_mode(sel, vga_mode);
TVE_set_vga_mode(sel);
Disp_TVEC_Open(sel);
TCON1_open(sel);
for (i = 0; i < 4; i++) {
if (gdisp.screen[sel].dac_source[i] ==
DISP_TV_DAC_SRC_COMPOSITE) {
TVE_dac_set_source(1 - sel, i,
DISP_TV_DAC_SRC_COMPOSITE);
TVE_dac_sel(1 - sel, i, i);
}
}
Disp_Switch_Dram_Mode(DISP_OUTPUT_TYPE_VGA, vga_mode);
gdisp.screen[sel].b_out_interlace = 0;
gdisp.screen[sel].status |= VGA_ON;
gdisp.screen[sel].lcdc_status |= LCDC_TCON1_USED;
gdisp.screen[sel].output_type = DISP_OUTPUT_TYPE_VGA;
Display_set_fb_timing(sel);
}
return DIS_SUCCESS;
}
__s32 BSP_disp_lcd_close_after(__u32 sel)
{
Image_close(sel);
Disp_lcdc_pin_cfg(sel, DISP_OUTPUT_TYPE_LCD, 0);
image_clk_off(sel);
lcdc_clk_off(sel);
gdisp.screen[sel].pll_use_status &= ((gdisp.screen[sel].pll_use_status == VIDEO_PLL0_USED)? VIDEO_PLL0_USED_MASK : VIDEO_PLL1_USED_MASK);
return DIS_SUCCESS;
}
__s32 BSP_disp_vga_close(__u32 sel)
{
if(gdisp.screen[sel].status & VGA_ON)
{
Image_close(sel);
TCON1_close(sel);
Disp_TVEC_Close(sel);
tve_clk_off(sel);
image_clk_off(sel);
lcdc_clk_off(sel);
Disp_lcdc_pin_cfg(sel, DISP_OUTPUT_TYPE_VGA, 0);
gdisp.screen[sel].b_out_interlace = 0;
gdisp.screen[sel].status &= VGA_OFF;
gdisp.screen[sel].lcdc_status &= LCDC_TCON1_USED_MASK;
gdisp.screen[sel].output_type = DISP_OUTPUT_TYPE_NONE;
gdisp.screen[sel].pll_use_status &= ((gdisp.screen[sel].pll_use_status == VIDEO_PLL0_USED)? VIDEO_PLL0_USED_MASK : VIDEO_PLL1_USED_MASK);
}
return DIS_SUCCESS;
}
__s32 BSP_disp_lcd_open_before(__u32 sel)
{
disp_clk_cfg(sel, DISP_OUTPUT_TYPE_LCD, 0);
lcdc_clk_on(sel);
image_clk_on(sel);
Image_open(sel);//set image normal channel start bit , because every de_clk_off( )will reset this bit
Disp_lcdc_pin_cfg(sel, DISP_OUTPUT_TYPE_LCD, 1);
if(gpanel_info[sel].tcon_index == 0)
{
TCON0_cfg(sel,(__ebios_panel_para_t*)&gpanel_info[sel]);
}
else
{
TCON1_cfg_ex(sel,(__ebios_panel_para_t*)&gpanel_info[sel]);
}
open_flow[sel].func_num = 0;
lcd_panel_fun[sel].cfg_open_flow(sel);
return DIS_SUCCESS;
}
__s32 LCD_POWER_EN(__u32 sel, __bool b_en)
{
#if 0
disp_gpio_set_t gpio_info[1];
__hdle hdl;
if(b_en)
{
if(gdisp.screen[sel].lcd_cfg.lcd_power_used)
{
if(gpanel_info[sel].lcd_if == LCD_IF_EXT_DSI)
{
LCD_POWER_ELDO3_EN(sel, 1, 12);
msleep(10);
}
memcpy(gpio_info, &(gdisp.screen[sel].lcd_cfg.lcd_power), sizeof(disp_gpio_set_t));
if(!b_en)
{
gpio_info->data = (gpio_info->data==0)?1:0;
}
hdl = OSAL_GPIO_Request(gpio_info, 1);
OSAL_GPIO_Release(hdl, 2);
udelay(200);
if((gpanel_info[sel].lcd_if == LCD_IF_EDP) && (gpanel_info[sel].lcd_edp_tx_ic == 0))
{
__u8 data;
__u32 ret;
__u8 addr;
addr = 0x1b;
data = 0x0b;
ret = ar100_axp_write_reg(&addr, &data, 1); //set eldo3 to 1.8v
if(ret != 0)
{
DE_WRN("set eldo3 to 1.8v fail\n");
}
addr = 0x12;
ret = ar100_axp_read_reg(&addr, &data, 1);
if(ret != 0)
{
DE_WRN("axp read reg fail\n");
}
addr = 0x12;
data |= 0x04;
ar100_axp_write_reg(&addr, &data, 1); //enable eldo3
if(ret != 0)
{
DE_WRN("enable eldo3 fail\n");
}
}
else if((gpanel_info[sel].lcd_if == LCD_IF_EDP) && (gpanel_info[sel].lcd_edp_tx_ic == 1))
{
__u8 data;
__u32 ret;
__u8 addr;
addr = 0x15;
data = 0x12;
ret = ar100_axp_write_reg(&addr, &data, 1); //set dldo1 to 2.5v
if(ret != 0)
{
DE_WRN("set dldo1 to 2.5v fail\n");
}
addr = 0x12;
ret = ar100_axp_read_reg(&addr, &data, 1);
if(ret != 0)
{
DE_WRN("axp read reg fail\n");
}
addr = 0x12;
data |= 0x08;
ar100_axp_write_reg(&addr, &data, 1); //enable dldo1
if(ret != 0)
{
DE_WRN("enable dldo1 fail\n");
}
addr = 0x1b;
data = 0x05;
ret = ar100_axp_write_reg(&addr, &data, 1); //set eldo3 to 1.2v
if(ret != 0)
{
DE_WRN("set eldo3 to 1.2v fail\n");
}
addr = 0x12;
ret = ar100_axp_read_reg(&addr, &data, 1);
if(ret != 0)
{
DE_WRN("axp read reg fail\n");
}
addr = 0x12;
data |= 0x04;
ar100_axp_write_reg(&addr, &data, 1); //enable eldo3
if(ret != 0)
{
DE_WRN("enable eldo3 fail\n");
}
}
msleep(50);
}
Disp_lcdc_pin_cfg(sel, DISP_OUTPUT_TYPE_LCD, 1);
msleep(2);
}
else
{
Disp_lcdc_pin_cfg(sel, DISP_OUTPUT_TYPE_LCD, 0);
msleep(2);
if(gdisp.screen[sel].lcd_cfg.lcd_power_used)
{
if((gpanel_info[sel].lcd_if == LCD_IF_EDP) && (gpanel_info[sel].lcd_edp_tx_ic == 0))
{
__u8 data;
__u32 ret;
__u8 addr;
addr = 0x12;
ret = ar100_axp_read_reg(&addr, &data, 1);
if(ret != 0)
{
DE_WRN("axp read reg fail\n");
}
data &= 0xfb;
ar100_axp_write_reg(&addr, &data, 1); //enable eldo3
if(ret != 0)
{
DE_WRN("disable eldo3 fail\n");
}
}
else if((gpanel_info[sel].lcd_if == LCD_IF_EDP) && (gpanel_info[sel].lcd_edp_tx_ic == 1))
{
__u8 data;
__u32 ret;
__u8 addr;
addr = 0x12;
ret = ar100_axp_read_reg(&addr, &data, 1);
if(ret != 0)
{
DE_WRN("axp read reg fail\n");
}
data &= 0xfb;
ar100_axp_write_reg(&addr, &data, 1); //disable eldo3
if(ret != 0)
{
DE_WRN("disable eldo3 fail\n");
}
addr = 0x12;
ret = ar100_axp_read_reg(&addr, &data, 1);
if(ret != 0)
{
DE_WRN("axp read reg fail\n");
}
data &= 0xf7;
ar100_axp_write_reg(&addr, &data, 1); //disable dldo1
if(ret != 0)
{
DE_WRN("disable dldo1 fail\n");
}
}
udelay(200);
memcpy(gpio_info, &(gdisp.screen[sel].lcd_cfg.lcd_power), sizeof(disp_gpio_set_t));
if(!b_en)
{
gpio_info->data = (gpio_info->data==0)?1:0;
}
hdl = OSAL_GPIO_Request(gpio_info, 1);
OSAL_GPIO_Release(hdl, 2);
if(gpanel_info[sel].lcd_if == LCD_IF_EXT_DSI)
{
LCD_POWER_ELDO3_EN(sel, 0, 7);
}
}
}
#endif
return 0;
}
