/**
* e1000_configure_rx - Configure 8254x Receive Unit after Reset
* @adapter: board private structure
*
* Configure the Rx unit of the MAC after a reset.
**/
static void e1000e_configure_rx ( struct e1000_adapter *adapter )
{
struct e1000_hw *hw = &adapter->hw;
uint32_t rctl;
DBGP ( "e1000_configure_rx\n" );
/* disable receives while setting up the descriptors */
rctl = E1000_READ_REG ( hw, E1000_RCTL );
E1000_WRITE_REG ( hw, E1000_RCTL, rctl & ~E1000_RCTL_EN );
e1e_flush();
mdelay(10);
adapter->rx_curr = 0;
/* Setup the HW Rx Head and Tail Descriptor Pointers and
* the Base and Length of the Rx Descriptor Ring */
E1000_WRITE_REG ( hw, E1000_RDBAL(0), virt_to_bus ( adapter->rx_base ) );
E1000_WRITE_REG ( hw, E1000_RDBAH(0), 0 );
E1000_WRITE_REG ( hw, E1000_RDLEN(0), adapter->rx_ring_size );
E1000_WRITE_REG ( hw, E1000_RDH(0), 0 );
E1000_WRITE_REG ( hw, E1000_RDT(0), NUM_RX_DESC - 1 );
/* Enable Receives */
rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_SZ_2048 |
E1000_RCTL_MPE;
E1000_WRITE_REG ( hw, E1000_RCTL, rctl );
e1e_flush();
DBG ( "E1000_RDBAL(0): %#08x\n", E1000_READ_REG ( hw, E1000_RDBAL(0) ) );
DBG ( "E1000_RDLEN(0): %d\n", E1000_READ_REG ( hw, E1000_RDLEN(0) ) );
DBG ( "E1000_RCTL: %#08x\n", E1000_READ_REG ( hw, E1000_RCTL ) );
}
void dna_cleanup_rx_ring(struct igb_ring *rx_ring) {
struct igb_adapter *adapter = netdev_priv(rx_ring->netdev);
struct e1000_hw *hw = &adapter->hw;
union e1000_adv_rx_desc *rx_desc, *shadow_rx_desc;
u32 head = E1000_READ_REG(hw, E1000_RDH(rx_ring->reg_idx));
u32 tail;
/*
tail = E1000_READ_REG(hw, E1000_RDT(rx_ring->reg_idx))
u32 count = rx_ring->count;
if(unlikely(enable_debug))
printk("[DNA] dna_cleanup_rx_ring(%d): [head=%u][tail=%u]\n", rx_ring->queue_index, head, tail);
// We now point to the next slot where packets will be received
if(++tail == rx_ring->count) tail = 0;
while(count > 0) {
if(tail == head) break; // Do not go beyond head
rx_desc = IGB_RX_DESC(rx_ring, tail);
shadow_rx_desc = IGB_RX_DESC(rx_ring, tail + rx_ring->count);
if(rx_desc->wb.upper.status_error != 0) {
print_adv_rx_descr(rx_desc);
break;
}
// Writeback
rx_desc->wb.upper.status_error = 0;
rx_desc->read.hdr_addr = shadow_rx_desc->read.hdr_addr, rx_desc->read.pkt_addr = shadow_rx_desc->read.pkt_addr;
E1000_WRITE_REG(hw, E1000_RDT(rx_ring->reg_idx), tail);
if(unlikely(enable_debug))
printk("[DNA] dna_cleanup_rx_ring(%d): idx=%d\n", rx_ring->queue_index, tail);
if(++tail == rx_ring->count) tail = 0;
count--;
}
*/
/* resetting all */
for (i=0; i<rx_ring->count; i++) {
rx_desc = IGB_RX_DESC(rx_ring, i);
shadow_rx_desc = IGB_RX_DESC(rx_ring, i + rx_ring->count);
rx_desc->wb.upper.status_error = 0;
rx_desc->read.hdr_addr = shadow_rx_desc->read.hdr_addr;
rx_desc->read.pkt_addr = shadow_rx_desc->read.pkt_addr;
}
if (head == 0) tail = rx_ring->count - 1;
else tail = head - 1;
E1000_WRITE_REG(hw, E1000_RDT(rx_ring->reg_idx), tail);
}
/*
* e1000g_rx_setup - setup rx data structures
*
* This routine initializes all of the receive related
* structures. This includes the receive descriptors, the
* actual receive buffers, and the rx_sw_packet software
* structures.
*/
void
e1000g_rx_setup(struct e1000g *Adapter)
{
struct e1000_hw *hw;
p_rx_sw_packet_t packet;
struct e1000_rx_desc *descriptor;
uint32_t buf_low;
uint32_t buf_high;
uint32_t reg_val;
uint32_t rctl;
uint32_t rxdctl;
uint32_t ert;
uint16_t phy_data;
int i;
int size;
e1000g_rx_data_t *rx_data;
hw = &Adapter->shared;
rx_data = Adapter->rx_ring->rx_data;
/*
* zero out all of the receive buffer descriptor memory
* assures any previous data or status is erased
*/
bzero(rx_data->rbd_area,
sizeof (struct e1000_rx_desc) * Adapter->rx_desc_num);
if (!Adapter->rx_buffer_setup) {
/* Init the list of "Receive Buffer" */
QUEUE_INIT_LIST(&rx_data->recv_list);
/* Init the list of "Free Receive Buffer" */
QUEUE_INIT_LIST(&rx_data->free_list);
/* Init the list of "Free Receive Buffer" */
QUEUE_INIT_LIST(&rx_data->recycle_list);
/*
* Setup Receive list and the Free list. Note that
* the both were allocated in one packet area.
*/
packet = rx_data->packet_area;
descriptor = rx_data->rbd_first;
for (i = 0; i < Adapter->rx_desc_num;
i++, packet = packet->next, descriptor++) {
ASSERT(packet != NULL);
ASSERT(descriptor != NULL);
descriptor->buffer_addr =
packet->rx_buf->dma_address;
/* Add this rx_sw_packet to the receive list */
QUEUE_PUSH_TAIL(&rx_data->recv_list,
&packet->Link);
}
for (i = 0; i < Adapter->rx_freelist_num;
i++, packet = packet->next) {
ASSERT(packet != NULL);
/* Add this rx_sw_packet to the free list */
QUEUE_PUSH_TAIL(&rx_data->free_list,
&packet->Link);
}
rx_data->avail_freepkt = Adapter->rx_freelist_num;
rx_data->recycle_freepkt = 0;
Adapter->rx_buffer_setup = B_TRUE;
} else {
/* Setup the initial pointer to the first rx descriptor */
packet = (p_rx_sw_packet_t)
QUEUE_GET_HEAD(&rx_data->recv_list);
descriptor = rx_data->rbd_first;
for (i = 0; i < Adapter->rx_desc_num; i++) {
ASSERT(packet != NULL);
ASSERT(descriptor != NULL);
descriptor->buffer_addr =
packet->rx_buf->dma_address;
/* Get next rx_sw_packet */
packet = (p_rx_sw_packet_t)
QUEUE_GET_NEXT(&rx_data->recv_list, &packet->Link);
descriptor++;
}
}
E1000_WRITE_REG(&Adapter->shared, E1000_RDTR, Adapter->rx_intr_delay);
E1000G_DEBUGLOG_1(Adapter, E1000G_INFO_LEVEL,
"E1000_RDTR: 0x%x\n", Adapter->rx_intr_delay);
if (hw->mac.type >= e1000_82540) {
E1000_WRITE_REG(&Adapter->shared, E1000_RADV,
Adapter->rx_intr_abs_delay);
E1000G_DEBUGLOG_1(Adapter, E1000G_INFO_LEVEL,
"E1000_RADV: 0x%x\n", Adapter->rx_intr_abs_delay);
}
/*
* Setup our descriptor pointers
*/
rx_data->rbd_next = rx_data->rbd_first;
size = Adapter->rx_desc_num * sizeof (struct e1000_rx_desc);
E1000_WRITE_REG(hw, E1000_RDLEN(0), size);
size = E1000_READ_REG(hw, E1000_RDLEN(0));
/* To get lower order bits */
buf_low = (uint32_t)rx_data->rbd_dma_addr;
/* To get the higher order bits */
buf_high = (uint32_t)(rx_data->rbd_dma_addr >> 32);
E1000_WRITE_REG(hw, E1000_RDBAH(0), buf_high);
E1000_WRITE_REG(hw, E1000_RDBAL(0), buf_low);
/*
* Setup our HW Rx Head & Tail descriptor pointers
*/
E1000_WRITE_REG(hw, E1000_RDT(0),
(uint32_t)(rx_data->rbd_last - rx_data->rbd_first));
E1000_WRITE_REG(hw, E1000_RDH(0), 0);
/*
* Setup the Receive Control Register (RCTL), and ENABLE the
* receiver. The initial configuration is to: Enable the receiver,
* accept broadcasts, discard bad packets (and long packets),
* disable VLAN filter checking, set the receive descriptor
* minimum threshold size to 1/2, and the receive buffer size to
* 2k.
*/
rctl = E1000_RCTL_EN | /* Enable Receive Unit */
E1000_RCTL_BAM | /* Accept Broadcast Packets */
E1000_RCTL_LPE | /* Large Packet Enable bit */
(hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT) |
E1000_RCTL_RDMTS_HALF |
E1000_RCTL_LBM_NO; /* Loopback Mode = none */
if (Adapter->strip_crc)
rctl |= E1000_RCTL_SECRC; /* Strip Ethernet CRC */
if (Adapter->mem_workaround_82546 &&
((hw->mac.type == e1000_82545) ||
(hw->mac.type == e1000_82546) ||
(hw->mac.type == e1000_82546_rev_3))) {
rctl |= E1000_RCTL_SZ_2048;
} else {
if ((Adapter->max_frame_size > FRAME_SIZE_UPTO_2K) &&
(Adapter->max_frame_size <= FRAME_SIZE_UPTO_4K))
rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
else if ((Adapter->max_frame_size > FRAME_SIZE_UPTO_4K) &&
(Adapter->max_frame_size <= FRAME_SIZE_UPTO_8K))
rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
else if ((Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) &&
(Adapter->max_frame_size <= FRAME_SIZE_UPTO_16K))
rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX;
else
rctl |= E1000_RCTL_SZ_2048;
}
if (e1000_tbi_sbp_enabled_82543(hw))
rctl |= E1000_RCTL_SBP;
/*
* Enable Early Receive Threshold (ERT) on supported devices.
* Only takes effect when packet size is equal or larger than the
* specified value (in 8 byte units), e.g. using jumbo frames.
*/
if ((hw->mac.type == e1000_82573) ||
(hw->mac.type == e1000_82574) ||
(hw->mac.type == e1000_ich9lan) ||
(hw->mac.type == e1000_ich10lan)) {
ert = E1000_ERT_2048;
/*
* Special modification when ERT and
* jumbo frames are enabled
*/
if (Adapter->default_mtu > ETHERMTU) {
rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 0x3);
ert |= (1 << 13);
}
E1000_WRITE_REG(hw, E1000_ERT, ert);
}
/* Workaround errata on 82577/8 adapters with large frames */
if ((hw->mac.type == e1000_pchlan) &&
(Adapter->default_mtu > ETHERMTU)) {
(void) e1000_read_phy_reg(hw, PHY_REG(770, 26), &phy_data);
phy_data &= 0xfff8;
phy_data |= (1 << 2);
(void) e1000_write_phy_reg(hw, PHY_REG(770, 26), phy_data);
if (hw->phy.type == e1000_phy_82577) {
(void) e1000_read_phy_reg(hw, 22, &phy_data);
phy_data &= 0x0fff;
phy_data |= (1 << 14);
(void) e1000_write_phy_reg(hw, 0x10, 0x2823);
(void) e1000_write_phy_reg(hw, 0x11, 0x0003);
(void) e1000_write_phy_reg(hw, 22, phy_data);
}
}
reg_val =
E1000_RXCSUM_TUOFL | /* TCP/UDP checksum offload Enable */
E1000_RXCSUM_IPOFL; /* IP checksum offload Enable */
E1000_WRITE_REG(hw, E1000_RXCSUM, reg_val);
/*
* Workaround: Set bit 16 (IPv6_ExDIS) to disable the
* processing of received IPV6 extension headers
*/
if ((hw->mac.type == e1000_82571) || (hw->mac.type == e1000_82572)) {
reg_val = E1000_READ_REG(hw, E1000_RFCTL);
reg_val |= (E1000_RFCTL_IPV6_EX_DIS |
E1000_RFCTL_NEW_IPV6_EXT_DIS);
E1000_WRITE_REG(hw, E1000_RFCTL, reg_val);
}
/* Write to enable the receive unit */
E1000_WRITE_REG(hw, E1000_RCTL, rctl);
}
/**
* e1000_translate_register_82542 - Translate the proper register offset
* @reg: e1000 register to be read
*
* Registers in 82542 are located in different offsets than other adapters
* even though they function in the same manner. This function takes in
* the name of the register to read and returns the correct offset for
* 82542 silicon.
**/
u32 e1000_translate_register_82542(u32 reg)
{
/*
* Some of the 82542 registers are located at different
* offsets than they are in newer adapters.
* Despite the difference in location, the registers
* function in the same manner.
*/
switch (reg) {
case E1000_RA:
reg = 0x00040;
break;
case E1000_RDTR:
reg = 0x00108;
break;
case E1000_RDBAL(0):
reg = 0x00110;
break;
case E1000_RDBAH(0):
reg = 0x00114;
break;
case E1000_RDLEN(0):
reg = 0x00118;
break;
case E1000_RDH(0):
reg = 0x00120;
break;
case E1000_RDT(0):
reg = 0x00128;
break;
case E1000_RDBAL(1):
reg = 0x00138;
break;
case E1000_RDBAH(1):
reg = 0x0013C;
break;
case E1000_RDLEN(1):
reg = 0x00140;
break;
case E1000_RDH(1):
reg = 0x00148;
break;
case E1000_RDT(1):
reg = 0x00150;
break;
case E1000_FCRTH:
reg = 0x00160;
break;
case E1000_FCRTL:
reg = 0x00168;
break;
case E1000_MTA:
reg = 0x00200;
break;
case E1000_TDBAL(0):
reg = 0x00420;
break;
case E1000_TDBAH(0):
reg = 0x00424;
break;
case E1000_TDLEN(0):
reg = 0x00428;
break;
case E1000_TDH(0):
reg = 0x00430;
break;
case E1000_TDT(0):
reg = 0x00438;
break;
case E1000_TIDV:
reg = 0x00440;
break;
case E1000_VFTA:
reg = 0x00600;
break;
case E1000_TDFH:
reg = 0x08010;
break;
case E1000_TDFT:
reg = 0x08018;
break;
default:
break;
}
return reg;
}
static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)
{
struct e1000_hw *hw = &adapter->hw;
struct e1000_mac_info *mac = &adapter->hw.mac;
u32 value;
u32 before;
u32 after;
u32 i;
u32 toggle;
u32 mask;
u32 wlock_mac = 0;
/*
* The status register is Read Only, so a write should fail.
* Some bits that get toggled are ignored.
*/
switch (mac->type) {
/* there are several bits on newer hardware that are r/w */
case e1000_82571:
case e1000_82572:
case e1000_80003es2lan:
toggle = 0x7FFFF3FF;
break;
default:
toggle = 0x7FFFF033;
break;
}
before = er32(STATUS);
value = (er32(STATUS) & toggle);
ew32(STATUS, toggle);
after = er32(STATUS) & toggle;
if (value != after) {
e_err("failed STATUS register test got: 0x%08X expected: 0x%08X\n",
after, value);
*data = 1;
return 1;
}
/* restore previous status */
ew32(STATUS, before);
if (!(adapter->flags & FLAG_IS_ICH)) {
REG_PATTERN_TEST(E1000_FCAL, 0xFFFFFFFF, 0xFFFFFFFF);
REG_PATTERN_TEST(E1000_FCAH, 0x0000FFFF, 0xFFFFFFFF);
REG_PATTERN_TEST(E1000_FCT, 0x0000FFFF, 0xFFFFFFFF);
REG_PATTERN_TEST(E1000_VET, 0x0000FFFF, 0xFFFFFFFF);
}
REG_PATTERN_TEST(E1000_RDTR, 0x0000FFFF, 0xFFFFFFFF);
REG_PATTERN_TEST(E1000_RDBAH(0), 0xFFFFFFFF, 0xFFFFFFFF);
REG_PATTERN_TEST(E1000_RDLEN(0), 0x000FFF80, 0x000FFFFF);
REG_PATTERN_TEST(E1000_RDH(0), 0x0000FFFF, 0x0000FFFF);
REG_PATTERN_TEST(E1000_RDT(0), 0x0000FFFF, 0x0000FFFF);
REG_PATTERN_TEST(E1000_FCRTH, 0x0000FFF8, 0x0000FFF8);
REG_PATTERN_TEST(E1000_FCTTV, 0x0000FFFF, 0x0000FFFF);
REG_PATTERN_TEST(E1000_TIPG, 0x3FFFFFFF, 0x3FFFFFFF);
REG_PATTERN_TEST(E1000_TDBAH(0), 0xFFFFFFFF, 0xFFFFFFFF);
REG_PATTERN_TEST(E1000_TDLEN(0), 0x000FFF80, 0x000FFFFF);
REG_SET_AND_CHECK(E1000_RCTL, 0xFFFFFFFF, 0x00000000);
before = ((adapter->flags & FLAG_IS_ICH) ? 0x06C3B33E : 0x06DFB3FE);
REG_SET_AND_CHECK(E1000_RCTL, before, 0x003FFFFB);
REG_SET_AND_CHECK(E1000_TCTL, 0xFFFFFFFF, 0x00000000);
REG_SET_AND_CHECK(E1000_RCTL, before, 0xFFFFFFFF);
REG_PATTERN_TEST(E1000_RDBAL(0), 0xFFFFFFF0, 0xFFFFFFFF);
if (!(adapter->flags & FLAG_IS_ICH))
REG_PATTERN_TEST(E1000_TXCW, 0xC000FFFF, 0x0000FFFF);
REG_PATTERN_TEST(E1000_TDBAL(0), 0xFFFFFFF0, 0xFFFFFFFF);
REG_PATTERN_TEST(E1000_TIDV, 0x0000FFFF, 0x0000FFFF);
mask = 0x8003FFFF;
switch (mac->type) {
case e1000_ich10lan:
case e1000_pchlan:
case e1000_pch2lan:
case e1000_pch_lpt:
mask |= (1 << 18);
break;
default:
break;
}
if (mac->type == e1000_pch_lpt)
wlock_mac = (er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK) >>
E1000_FWSM_WLOCK_MAC_SHIFT;
for (i = 0; i < mac->rar_entry_count; i++) {
/* Cannot test write-protected SHRAL[n] registers */
if ((wlock_mac == 1) || (wlock_mac && (i > wlock_mac)))
continue;
REG_PATTERN_TEST_ARRAY(E1000_RA, ((i << 1) + 1),
mask, 0xFFFFFFFF);
}
for (i = 0; i < mac->mta_reg_count; i++)
REG_PATTERN_TEST_ARRAY(E1000_MTA, i, 0xFFFFFFFF, 0xFFFFFFFF);
*data = 0;
return 0;
}
/*
* mac_dump - dump important mac registers
*/
void
mac_dump(void *instance)
{
struct e1000g *Adapter = (struct e1000g *)instance;
struct e1000_hw *hw = &Adapter->shared;
int i;
/* {name, offset} for each mac register */
Regi_t macreg[NUM_REGS] = {
{"CTRL", E1000_CTRL}, {"STATUS", E1000_STATUS},
{"EECD", E1000_EECD}, {"EERD", E1000_EERD},
{"CTRL_EXT", E1000_CTRL_EXT}, {"FLA", E1000_FLA},
{"MDIC", E1000_MDIC}, {"SCTL", E1000_SCTL},
{"FCAL", E1000_FCAL}, {"FCAH", E1000_FCAH},
{"FCT", E1000_FCT}, {"VET", E1000_VET},
{"ICR", E1000_ICR}, {"ITR", E1000_ITR},
{"ICS", E1000_ICS}, {"IMS", E1000_IMS},
{"IMC", E1000_IMC}, {"IAM", E1000_IAM},
{"RCTL", E1000_RCTL}, {"FCTTV", E1000_FCTTV},
{"TXCW", E1000_TXCW}, {"RXCW", E1000_RXCW},
{"TCTL", E1000_TCTL}, {"TIPG", E1000_TIPG},
{"AIT", E1000_AIT}, {"LEDCTL", E1000_LEDCTL},
{"PBA", E1000_PBA}, {"PBS", E1000_PBS},
{"EEMNGCTL", E1000_EEMNGCTL}, {"ERT", E1000_ERT},
{"FCRTL", E1000_FCRTL}, {"FCRTH", E1000_FCRTH},
{"PSRCTL", E1000_PSRCTL}, {"RDBAL(0)", E1000_RDBAL(0)},
{"RDBAH(0)", E1000_RDBAH(0)}, {"RDLEN(0)", E1000_RDLEN(0)},
{"RDH(0)", E1000_RDH(0)}, {"RDT(0)", E1000_RDT(0)},
{"RDTR", E1000_RDTR}, {"RXDCTL(0)", E1000_RXDCTL(0)},
{"RADV", E1000_RADV}, {"RDBAL(1)", E1000_RDBAL(1)},
{"RDBAH(1)", E1000_RDBAH(1)}, {"RDLEN(1)", E1000_RDLEN(1)},
{"RDH(1)", E1000_RDH(1)}, {"RDT(1)", E1000_RDT(1)},
{"RXDCTL(1)", E1000_RXDCTL(1)}, {"RSRPD", E1000_RSRPD},
{"RAID", E1000_RAID}, {"CPUVEC", E1000_CPUVEC},
{"TDFH", E1000_TDFH}, {"TDFT", E1000_TDFT},
{"TDFHS", E1000_TDFHS}, {"TDFTS", E1000_TDFTS},
{"TDFPC", E1000_TDFPC}, {"TDBAL(0)", E1000_TDBAL(0)},
{"TDBAH(0)", E1000_TDBAH(0)}, {"TDLEN(0)", E1000_TDLEN(0)},
{"TDH(0)", E1000_TDH(0)}, {"TDT(0)", E1000_TDT(0)},
{"TIDV", E1000_TIDV}, {"TXDCTL(0)", E1000_TXDCTL(0)},
{"TADV", E1000_TADV}, {"TARC(0)", E1000_TARC(0)},
{"TDBAL(1)", E1000_TDBAL(1)}, {"TDBAH(1)", E1000_TDBAH(1)},
{"TDLEN(1)", E1000_TDLEN(1)}, {"TDH(1)", E1000_TDH(1)},
{"TDT(1)", E1000_TDT(1)}, {"TXDCTL(1)", E1000_TXDCTL(1)},
{"TARC(1)", E1000_TARC(1)}, {"ALGNERRC", E1000_ALGNERRC},
{"RXERRC", E1000_RXERRC}, {"MPC", E1000_MPC},
{"SCC", E1000_SCC}, {"ECOL", E1000_ECOL},
{"MCC", E1000_MCC}, {"LATECOL", E1000_LATECOL},
{"COLC", E1000_COLC}, {"DC", E1000_DC},
{"TNCRS", E1000_TNCRS}, {"SEC", E1000_SEC},
{"CEXTERR", E1000_CEXTERR}, {"RLEC", E1000_RLEC},
{"XONRXC", E1000_XONRXC}, {"XONTXC", E1000_XONTXC},
{"XOFFRXC", E1000_XOFFRXC}, {"XOFFTXC", E1000_XOFFTXC},
{"FCRUC", E1000_FCRUC}, {"PRC64", E1000_PRC64},
{"PRC127", E1000_PRC127}, {"PRC255", E1000_PRC255},
{"PRC511", E1000_PRC511}, {"PRC1023", E1000_PRC1023},
{"PRC1522", E1000_PRC1522}, {"GPRC", E1000_GPRC},
{"BPRC", E1000_BPRC}, {"MPRC", E1000_MPRC},
{"GPTC", E1000_GPTC}, {"GORCL", E1000_GORCL},
{"GORCH", E1000_GORCH}, {"GOTCL", E1000_GOTCL},
{"GOTCH", E1000_GOTCH}, {"RNBC", E1000_RNBC},
{"RUC", E1000_RUC}, {"RFC", E1000_RFC},
{"ROC", E1000_ROC}, {"RJC", E1000_RJC},
{"MGTPRC", E1000_MGTPRC}, {"MGTPDC", E1000_MGTPDC},
{"MGTPTC", E1000_MGTPTC}, {"TORL", E1000_TORL},
{"TORH", E1000_TORH}, {"TOTL", E1000_TOTL},
{"TOTH", E1000_TOTH}, {"TPR", E1000_TPR},
{"TPT", E1000_TPT}, {"PTC64", E1000_PTC64},
{"PTC127", E1000_PTC127}, {"PTC255", E1000_PTC255},
{"PTC511", E1000_PTC511}, {"PTC1023", E1000_PTC1023},
{"PTC1522", E1000_PTC1522}, {"MPTC", E1000_MPTC},
{"BPTC", E1000_BPTC}, {"TSCTC", E1000_TSCTC},
{"TSCTFC", E1000_TSCTFC}, {"IAC", E1000_IAC},
{"ICRXPTC", E1000_ICRXPTC}, {"ICRXATC", E1000_ICRXATC},
{"ICTXPTC", E1000_ICTXPTC}, {"ICTXATC", E1000_ICTXATC},
{"ICTXQEC", E1000_ICTXQEC}, {"ICTXQMTC", E1000_ICTXQMTC},
{"ICRXDMTC", E1000_ICRXDMTC}, {"ICRXOC", E1000_ICRXOC},
{"RXCSUM", E1000_RXCSUM}, {"RFCTL", E1000_RFCTL},
{"WUC", E1000_WUC}, {"WUFC", E1000_WUFC},
{"WUS", E1000_WUS}, {"MRQC", E1000_MRQC},
{"MANC", E1000_MANC}, {"IPAV", E1000_IPAV},
{"MANC2H", E1000_MANC2H}, {"RSSIM", E1000_RSSIM},
{"RSSIR", E1000_RSSIR}, {"WUPL", E1000_WUPL},
{"GCR", E1000_GCR}, {"GSCL_1", E1000_GSCL_1},
{"GSCL_2", E1000_GSCL_2}, {"GSCL_3", E1000_GSCL_3},
{"GSCL_4", E1000_GSCL_4}, {"FACTPS", E1000_FACTPS},
{"FWSM", E1000_FWSM},
};
e1000g_log(Adapter, CE_CONT, "Begin MAC dump\n");
for (i = 0; i < NUM_REGS; i++) {
e1000g_log(Adapter, CE_CONT,
"macreg %10s offset: 0x%x value: 0x%x\n",
macreg[i].name, macreg[i].offset,
e1000_read_reg(hw, macreg[i].offset));
}
}
/*------------------------------------------------------------------------
* _82545EM_configure_rx - Configure Receive Unit after Reset
*------------------------------------------------------------------------
*/
local void _82545EM_configure_rx(
struct ether *ethptr
)
{
uint32 rctl, rxcsum;
rctl = e1000_io_readl(ethptr->iobase, E1000_RCTL);
/* Disable receiver while configuring. */
e1000_io_writel(ethptr->iobase, E1000_RCTL, rctl & ~E1000_RCTL_EN);
/* Enable receiver, accept broadcast packets, no loopback, and */
/* free buffer threshold is set to 1/2 RDLEN. */
rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
rctl |= E1000_RCTL_EN |
E1000_RCTL_BAM |
E1000_RCTL_LBM_NO |
E1000_RCTL_RDMTS_HALF;
/* Do not store bad packets, do not pass MAC control frame, */
/* disable long packet receive and CRC strip */
rctl &= ~(E1000_RCTL_SBP |
E1000_RCTL_LPE |
E1000_RCTL_SECRC |
E1000_RCTL_PMCF);
/* Setup buffer sizes */
rctl &= ~(E1000_RCTL_BSEX |
E1000_RCTL_SZ_4096);
rctl |= E1000_RCTL_SZ_2048;
/* Set the Receive Delay Timer Register, let driver be notified */
/* immediately each time a new packet has been stored in */
/* memory */
e1000_io_writel(ethptr->iobase, E1000_RDTR, E1000_RDTR_DEFAULT);
e1000_io_writel(ethptr->iobase, E1000_RADV, E1000_RADV_DEFAULT);
/* IRQ moderation */
e1000_io_writel(ethptr->iobase, E1000_ITR,
1000000000 / (E1000_ITR_DEFAULT * 256));
/* Setup the HW Rx Head and Tail Descriptor Pointers, the Base */
/* and Length of the Rx Descriptor Ring */
e1000_io_writel(ethptr->iobase, E1000_RDBAL(0),
(uint32)ethptr->rxRing);
e1000_io_writel(ethptr->iobase, E1000_RDBAH(0), 0);
e1000_io_writel(ethptr->iobase, E1000_RDLEN(0),
E1000_RDSIZE * ethptr->rxRingSize);
e1000_io_writel(ethptr->iobase, E1000_RDH(0), 0);
e1000_io_writel(ethptr->iobase, E1000_RDT(0),
ethptr->rxRingSize - E1000_RING_BOUNDARY);
/* Disable Receive Checksum Offload for IPv4, TCP and UDP. */
rxcsum = e1000_io_readl(ethptr->iobase, E1000_RXCSUM);
rxcsum &= ~(E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL);
e1000_io_writel(ethptr->iobase, E1000_RXCSUM, rxcsum);
/* Enable receiver. */
e1000_io_writel(ethptr->iobase, E1000_RCTL, rctl);
}