int board_early_init_f (void) { unsigned long mfr; /*-------------------------------------------------------------------------+ | Initialize EBC CONFIG +-------------------------------------------------------------------------*/ mtebc(xbcfg, EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT | EBC_CFG_PME_DISABLE | EBC_CFG_PR_32); /*-------------------------------------------------------------------------+ | 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values. +-------------------------------------------------------------------------*/ mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(8)| EBC_BXAP_BCE_DISABLE| EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| EBC_BXAP_BEM_WRITEONLY| EBC_BXAP_PEN_DISABLED); mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(0xFFE00000)| EBC_BXCR_BS_2MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); /*-------------------------------------------------------------------------+ | 8KB NVRAM/RTC. Initialize bank 1 with default values. +-------------------------------------------------------------------------*/ mtebc(pb1ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)| EBC_BXAP_BCE_DISABLE| EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| EBC_BXAP_BEM_WRITEONLY| EBC_BXAP_PEN_DISABLED); mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000)| EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); /*-------------------------------------------------------------------------+ | 4 MB FLASH. Initialize bank 2 with default values. +-------------------------------------------------------------------------*/ mtebc(pb2ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)| EBC_BXAP_BCE_DISABLE| EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| EBC_BXAP_BEM_WRITEONLY| EBC_BXAP_PEN_DISABLED); mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xFF800000)| EBC_BXCR_BS_4MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); /*-------------------------------------------------------------------------+ | FPGA. Initialize bank 7 with default values. +-------------------------------------------------------------------------*/ mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)| EBC_BXAP_BCE_DISABLE| EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| EBC_BXAP_BEM_WRITEONLY| EBC_BXAP_PEN_DISABLED); mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)| EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. *-------------------------------------------------------------------*/ mtdcr (uic0sr, 0xffffffff); /* clear all */ mtdcr (uic0er, 0x00000000); /* disable all */ mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */ mtdcr (uic0pr, 0xfffffe13); /* per ref-board manual */ mtdcr (uic0tr, 0x01c00008); /* per ref-board manual */ mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr (uic0sr, 0xffffffff); /* clear all */ mtdcr (uic1sr, 0xffffffff); /* clear all */ mtdcr (uic1er, 0x00000000); /* disable all */ mtdcr (uic1cr, 0x00000000); /* all non-critical */ mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */ mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */ mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr (uic1sr, 0xffffffff); /* clear all */ mtdcr (uic2sr, 0xffffffff); /* clear all */ mtdcr (uic2er, 0x00000000); /* disable all */ mtdcr (uic2cr, 0x00000000); /* all non-critical */ mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */ mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */ mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr (uic2sr, 0xffffffff); /* clear all */ mtdcr (uicb0sr, 0xfc000000); /* clear all */ mtdcr (uicb0er, 0x00000000); /* disable all */ mtdcr (uicb0cr, 0x00000000); /* all non-critical */ mtdcr (uicb0pr, 0xfc000000); /* */ mtdcr (uicb0tr, 0x00000000); /* */ mtdcr (uicb0vr, 0x00000001); /* */ mfsdr (sdr_mfr, mfr); mfr &= ~SDR0_MFR_ECS_MASK; /* mtsdr(sdr_mfr, mfr); */ fpga_init(); return 0; }
int board_early_init_f (void) { unsigned long mfr; unsigned char *fpga_base = (unsigned char *) CONFIG_SYS_FPGA_BASE; unsigned char switch_status; unsigned long cs0_base; unsigned long cs0_size; unsigned long cs0_twt; unsigned long cs2_base; unsigned long cs2_size; unsigned long cs2_twt; /*-------------------------------------------------------------------------+ | Initialize EBC CONFIG +-------------------------------------------------------------------------*/ mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT | EBC_CFG_PME_DISABLE | EBC_CFG_PR_32); /*-------------------------------------------------------------------------+ | FPGA. Initialize bank 7 with default values. +-------------------------------------------------------------------------*/ mtebc(PB7AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)| EBC_BXAP_BCE_DISABLE| EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| EBC_BXAP_BEM_WRITEONLY| EBC_BXAP_PEN_DISABLED); mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48300000)| EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); /* read FPGA base register FPGA_REG0 */ switch_status = *fpga_base; if (switch_status & 0x40) { cs0_base = 0xFFE00000; cs0_size = EBC_BXCR_BS_2MB; cs0_twt = 8; cs2_base = 0xFF800000; cs2_size = EBC_BXCR_BS_4MB; cs2_twt = 10; } else { cs0_base = 0xFFC00000; cs0_size = EBC_BXCR_BS_4MB; cs0_twt = 10; cs2_base = 0xFF800000; cs2_size = EBC_BXCR_BS_2MB; cs2_twt = 8; } /*-------------------------------------------------------------------------+ | 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values. +-------------------------------------------------------------------------*/ mtebc(PB0AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)| EBC_BXAP_BCE_DISABLE| EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| EBC_BXAP_BEM_WRITEONLY| EBC_BXAP_PEN_DISABLED); mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(cs0_base)| cs0_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); /*-------------------------------------------------------------------------+ | 8KB NVRAM/RTC. Initialize bank 1 with default values. +-------------------------------------------------------------------------*/ mtebc(PB1AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)| EBC_BXAP_BCE_DISABLE| EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| EBC_BXAP_BEM_WRITEONLY| EBC_BXAP_PEN_DISABLED); mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000)| EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); /*-------------------------------------------------------------------------+ | 4 MB FLASH. Initialize bank 2 with default values. +-------------------------------------------------------------------------*/ mtebc(PB2AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)| EBC_BXAP_BCE_DISABLE| EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| EBC_BXAP_BEM_WRITEONLY| EBC_BXAP_PEN_DISABLED); mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(cs2_base)| cs2_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); /*-------------------------------------------------------------------------+ | FPGA. Initialize bank 7 with default values. +-------------------------------------------------------------------------*/ mtebc(PB7AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)| EBC_BXAP_BCE_DISABLE| EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| EBC_BXAP_BEM_WRITEONLY| EBC_BXAP_PEN_DISABLED); mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48300000)| EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. *-------------------------------------------------------------------*/ /* * Because of the interrupt handling rework to handle 440GX interrupts * with the common code, we needed to change names of the UIC registers. * Here the new relationship: * * U-Boot name 440GX name * ----------------------- * UIC0 UICB0 * UIC1 UIC0 * UIC2 UIC1 * UIC3 UIC2 */ mtdcr (UIC1SR, 0xffffffff); /* clear all */ mtdcr (UIC1ER, 0x00000000); /* disable all */ mtdcr (UIC1CR, 0x00000009); /* SMI & UIC1 crit are critical */ mtdcr (UIC1PR, 0xfffffe13); /* per ref-board manual */ mtdcr (UIC1TR, 0x01c00008); /* per ref-board manual */ mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ mtdcr (UIC1SR, 0xffffffff); /* clear all */ mtdcr (UIC2SR, 0xffffffff); /* clear all */ mtdcr (UIC2ER, 0x00000000); /* disable all */ mtdcr (UIC2CR, 0x00000000); /* all non-critical */ mtdcr (UIC2PR, 0xffffe0ff); /* per ref-board manual */ mtdcr (UIC2TR, 0x00ffc000); /* per ref-board manual */ mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */ mtdcr (UIC2SR, 0xffffffff); /* clear all */ mtdcr (UIC3SR, 0xffffffff); /* clear all */ mtdcr (UIC3ER, 0x00000000); /* disable all */ mtdcr (UIC3CR, 0x00000000); /* all non-critical */ mtdcr (UIC3PR, 0xffffffff); /* per ref-board manual */ mtdcr (UIC3TR, 0x00ff8c0f); /* per ref-board manual */ mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */ mtdcr (UIC3SR, 0xffffffff); /* clear all */ mtdcr (UIC0SR, 0xfc000000); /* clear all */ mtdcr (UIC0ER, 0x00000000); /* disable all */ mtdcr (UIC0CR, 0x00000000); /* all non-critical */ mtdcr (UIC0PR, 0xfc000000); /* */ mtdcr (UIC0TR, 0x00000000); /* */ mtdcr (UIC0VR, 0x00000001); /* */ mfsdr (SDR0_MFR, mfr); mfr &= ~SDR0_MFR_ECS_MASK; /* mtsdr(SDR0_MFR, mfr); */ fpga_init(); return 0; }
int board_early_init_f (void) { unsigned long reg; volatile unsigned int *GpioOdr; volatile unsigned int *GpioTcr; volatile unsigned int *GpioOr; /*-------------------------------------------------------------------------+ | Initialize EBC CONFIG +-------------------------------------------------------------------------*/ mtebc(xbcfg, EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE | EBC_CFG_PR_32); /*-------------------------------------------------------------------------+ | 64MB FLASH. Initialize bank 0 with default values. +-------------------------------------------------------------------------*/ mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(15) | EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) | EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) | EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_32BIT); /*-------------------------------------------------------------------------+ | FPGA. Initialize bank 1 with default values. +-------------------------------------------------------------------------*/ mtebc(pb1ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(5) | EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) | EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x41000000) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); /*-------------------------------------------------------------------------+ | LCM. Initialize bank 2 with default values. +-------------------------------------------------------------------------*/ mtebc(pb2ap, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(64) | EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) | EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) | EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0x42000000) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); /*-------------------------------------------------------------------------+ | TMP. Initialize bank 3 with default values. +-------------------------------------------------------------------------*/ mtebc(pb3ap, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(128) | EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) | EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) | EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48000000) | EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); /*-------------------------------------------------------------------------+ | Connector 4~7. Initialize bank 3~ 7 with default values. +-------------------------------------------------------------------------*/ mtebc(pb4ap,0); mtebc(pb4cr,0); mtebc(pb5ap,0); mtebc(pb5cr,0); mtebc(pb6ap,0); mtebc(pb6cr,0); mtebc(pb7ap,0); mtebc(pb7cr,0); /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. *-------------------------------------------------------------------*/ /* * Because of the interrupt handling rework to handle 440GX interrupts * with the common code, we needed to change names of the UIC registers. * Here the new relationship: * * U-Boot name 440GX name * ----------------------- * UIC0 UICB0 * UIC1 UIC0 * UIC2 UIC1 * UIC3 UIC2 */ mtdcr (uic1sr, 0xffffffff); /* clear all */ mtdcr (uic1er, 0x00000000); /* disable all */ mtdcr (uic1cr, 0x00000009); /* SMI & UIC1 crit are critical */ mtdcr (uic1pr, 0xfffffe13); /* per ref-board manual */ mtdcr (uic1tr, 0x01c00008); /* per ref-board manual */ mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr (uic1sr, 0xffffffff); /* clear all */ mtdcr (uic2sr, 0xffffffff); /* clear all */ mtdcr (uic2er, 0x00000000); /* disable all */ mtdcr (uic2cr, 0x00000000); /* all non-critical */ mtdcr (uic2pr, 0xffffe0ff); /* per ref-board manual */ mtdcr (uic2tr, 0x00ffc000); /* per ref-board manual */ mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr (uic2sr, 0xffffffff); /* clear all */ mtdcr (uic3sr, 0xffffffff); /* clear all */ mtdcr (uic3er, 0x00000000); /* disable all */ mtdcr (uic3cr, 0x00000000); /* all non-critical */ mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */ mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */ mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr (uic3sr, 0xffffffff); /* clear all */ mtdcr (uic0sr, 0xfc000000); /* clear all */ mtdcr (uic0er, 0x00000000); /* disable all */ mtdcr (uic0cr, 0x00000000); /* all non-critical */ mtdcr (uic0pr, 0xfc000000); /* */ mtdcr (uic0tr, 0x00000000); /* */ mtdcr (uic0vr, 0x00000001); /* */ /* Enable two GPIO 10~11 and TraceA signal */ mfsdr(sdr_pfc0,reg); reg |= 0x00300000; mtsdr(sdr_pfc0,reg); mfsdr(sdr_pfc1,reg); reg |= 0x00100000; mtsdr(sdr_pfc1,reg); /* Set GPIO 10 and 11 as output */ GpioOdr = (volatile unsigned int*)(CFG_PERIPHERAL_BASE+0x718); GpioTcr = (volatile unsigned int*)(CFG_PERIPHERAL_BASE+0x704); GpioOr = (volatile unsigned int*)(CFG_PERIPHERAL_BASE+0x700); *GpioOdr &= ~(0x00300000); *GpioTcr |= 0x00300000; *GpioOr |= 0x00300000; return 0; }