/** ESC reset hardware. */ void ESC_reset (void) { /* disable ESC to force reset */ ESC_disable (); /* initialize EEPROM emulation */ EEP_init (); }
// basic module initialization void BSC_init(void) { frame_t fr; // fifoes init FIFO_init(&BSC.in_fifo, &BSC.in_buf, NB_IN_FRAMES, sizeof(frame_t)); FIFO_init(&BSC.out_fifo, &BSC.out_buf, NB_OUT_FRAMES, sizeof(frame_t)); // thread init PT_INIT(&BSC.in_pt); PT_INIT(&BSC.out_pt); // reset time-out BSC.time_out = 0; BSC.is_running = FALSE; // register own call-back for specific commands BSC.interf.channel = 0; BSC.interf.cmde_mask = _CM(FR_NO_CMDE) | _CM(FR_RAM_READ) | _CM(FR_RAM_WRITE) | _CM(FR_EEP_READ) | _CM(FR_EEP_WRITE) | _CM(FR_FLH_READ) | _CM(FR_FLH_WRITE) | _CM(FR_SPI_READ) | _CM(FR_SPI_WRITE) | _CM(FR_WAIT) | _CM(FR_CONTAINER); BSC.interf.queue = &BSC.in_fifo; DPT_register(&BSC.interf); // drivers init SLP_init(); EEP_init(); SPI_init(SPI_MASTER, SPI_THREE, SPI_MSB, SPI_DIV_16); // read reset frame EEP_read(0x00, (u8*)&fr, sizeof(frame_t)); while ( ! EEP_is_fini() ) ; // check if the frame is valid if ( fr.dest == 0xff || fr.orig == 0xff || fr.cmde == 0xff || fr.status == 0xff ) { return; } // enqueue the reset frame FIFO_put(&BSC.out_fifo, &fr); // lock the dispatcher to be able to treat the frame DPT_lock(&BSC.interf); }