{
	int i;

	/* Setup system level pin muxing */
	for (i = 0; i < (sizeof(pinmuxing) / sizeof(pinmuxing[0])); i++) {
		Chip_SCU_PinMux(pinmuxing[i].pingrp, pinmuxing[i].pinnum,
						pinmuxing[i].pincfg, pinmuxing[i].funcnum);
	}
}

/* EMC clock delay */
#define CLK0_DELAY 7

/* Hitex SDRAM timing and chip Config */
STATIC const IP_EMC_DYN_CONFIG_Type IS42S16400_config = {
	EMC_NANOSECOND(64000000 / 4096),	/* Row refresh time */
	0x01,	/* Command Delayed */
	EMC_NANOSECOND(20),
	EMC_NANOSECOND(60),
	EMC_NANOSECOND(63),
	EMC_CLOCK(0x05),
	EMC_CLOCK(0x05),
	EMC_CLOCK(0x04),
	EMC_NANOSECOND(63),
	EMC_NANOSECOND(63),
	EMC_NANOSECOND(63),
	EMC_NANOSECOND(14),
	EMC_CLOCK(0x02),
	{
		{
			EMC_ADDRESS_DYCS0,	/* Hitex Board uses DYCS0 for SDRAM */
예제 #2
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	for (i = 0; i < (sizeof(pinmuxing) / sizeof(pinmuxing[0])); i++) {
		Chip_SCU_PinMuxSet(pinmuxing[i].pingrp, pinmuxing[i].pinnum,
						   pinmuxing[i].modefunc);
	}
	/* Clock pins only, group field not used */
	for (i = 0; i < (sizeof(pinclockmuxing) / sizeof(pinclockmuxing[0])); i++) {
		Chip_SCU_ClockPinMuxSet(pinclockmuxing[i].pinnum, pinclockmuxing[i].modefunc);
	}
}

/* EMC clock delay */
#define CLK0_DELAY 7

/* Keil SDRAM timing and chip Config */
STATIC const IP_EMC_DYN_CONFIG_T MT48LC4M32_config = {
	EMC_NANOSECOND(64000000 / 4096),	/* Row refresh time */
	0x01,	/* Command Delayed */
	EMC_NANOSECOND(18),
	EMC_NANOSECOND(42),
	EMC_NANOSECOND(70),
	EMC_CLOCK(0x01),
	EMC_CLOCK(0x05),
	EMC_NANOSECOND(12),
	EMC_NANOSECOND(60),
	EMC_NANOSECOND(60),
	EMC_NANOSECOND(70),
	EMC_NANOSECOND(12),
	EMC_CLOCK(0x02),
	{
		{
			EMC_ADDRESS_DYCS0,	/* Keil Board uses DYCS0 for SDRAM */