//================================================================================
// EMU_enter_DefaultMode_from_RESET
//================================================================================
extern void EMU_enter_DefaultMode_from_RESET(void) {
// $[EMU Initialization]
/* Initialize DCDC regulator */
EMU_DCDCInit_TypeDef dcdcInit = EMU_DCDCINIT_DEFAULT;
dcdcInit.powerConfig = emuPowerConfig_DcdcToDvdd;
dcdcInit.dcdcMode = emuDcdcMode_LowNoise;
dcdcInit.mVout = 1800;
dcdcInit.em01LoadCurrent_mA = 15;
dcdcInit.em234LoadCurrent_uA = 10;
dcdcInit.maxCurrent_mA = 200;
dcdcInit.anaPeripheralPower = emuDcdcAnaPeripheralPower_DCDC;
dcdcInit.reverseCurrentControl = 160;
EMU_DCDCInit(&dcdcInit);
/* Initialize EM2/EM3 mode */
EMU_EM23Init_TypeDef em23Init = EMU_EM23INIT_DEFAULT;
em23Init.em23VregFullEn = 0;
EMU_EM23Init(&em23Init);
/* Initialize EM4H/S mode */
EMU_EM4Init_TypeDef em4Init = EMU_EM4INIT_DEFAULT;
em4Init.retainLfrco = 0;
em4Init.retainLfxo = 0;
em4Init.retainUlfrco = 0;
em4Init.em4State = emuEM4Shutoff;
em4Init.pinRetentionMode = emuPinRetentionDisable;
EMU_EM4Init(&em4Init);
// [EMU Initialization]$
}
void lpm_arch_init(void)
{
/* initialize EM2 and EM3 */
EMU_EM23Init_TypeDef init_em23 = EMU_EM23INIT_DEFAULT;
EMU_EM23Init(&init_em23);
#ifdef _SILICON_LABS_32B_PLATFORM_2
/* initialize EM4 */
EMU_EM4Init_TypeDef init_em4 = EMU_EM4INIT_DEFAULT;
EMU_EM4Init(&init_em4);
#endif
}
void main ()
{
uint32_t lfa_Hz;
uint16_t reset_cause;
int sleep_mode = 0;
uint32_t burtc_ctrl;
CHIP_Init();
reset_cause = RMU->RSTCAUSE;
RMU_ResetCauseClear();
#if ! defined(_EFM32_ZERO_FAMILY)
BSPACM_CORE_BITBAND_PERIPH(RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT) = 0;
#endif
SystemCoreClockUpdate();
vBSPACMledConfigure();
setvbuf(stdout, NULL, _IONBF, 0);
BSPACM_CORE_ENABLE_INTERRUPT();
printf("\n" __DATE__ " " __TIME__ "\n");
printf("System clock %lu Hz\n", SystemCoreClock);
{
int i = sizeof(xResetCause)/sizeof(*xResetCause);
printf("Reset cause [%04x]:", reset_cause);
while (0 <= --i) {
const sResetCause * const rcp = xResetCause + i;
if (rcp->value == (reset_cause & rcp->mask)) {
printf(" %s", rcp->name);
}
}
printf("\nRMU CTRL %lx\n", RMU->CTRL);
}
/* Enable low-energy support. */
CMU_ClockEnable(cmuClock_CORELE, true);
BURTC_Enable(true);
if (MAGIC != retained_state->magic) {
memset(retained_state, 0, sizeof(*retained_state));
retained_state->magic = MAGIC;
printf("Resetting retained state\n");
}
++retained_state->boots;
printf("Boot count %lu\n", retained_state->boots);
printf("BURTC clock source: ");
#if (WITH_ULFRCO - 0)
/* Use ULFRCO, which enables EM4 wakeup but is pretty inaccurate. */
printf("ULFRCO\n");
/* NB: DIV2 means 1 kHz instead of 2 kHz */
burtc_ctrl = BURTC_CTRL_CLKSEL_ULFRCO | BURTC_CTRL_PRESC_DIV2;
CMU_ClockSelectSet(cmuClock_LFA, cmuSelect_ULFRCO);
lfa_Hz = CMU_ClockFreqGet(cmuClock_LFA);
{
EMU_EM4Init_TypeDef cfg = {
.lockConfig = 1,
.osc = EMU_EM4CONF_OSC_ULFRCO,
.buRtcWakeup = 1,
.vreg = 1,
};
EMU_EM4Init(&cfg);
}
#elif (WITH_LFRCO - 0)
printf("LFRCO/32\n");
CMU_ClockSelectSet(cmuClock_LFA, cmuSelect_LFRCO);
burtc_ctrl = BURTC_CTRL_CLKSEL_LFRCO | BURTC_CTRL_PRESC_DIV32;
lfa_Hz = CMU_ClockFreqGet(cmuClock_LFA) / 32;
#else
printf("LFXO/32\n");
CMU_ClockSelectSet(cmuClock_LFA, cmuSelect_LFXO);
burtc_ctrl = BURTC_CTRL_CLKSEL_LFXO | BURTC_CTRL_PRESC_DIV32;
lfa_Hz = CMU_ClockFreqGet(cmuClock_LFA) / 32;
#endif /* LFA source */
printf("LFA clock at %lu Hz ; wake every %u seconds\n", lfa_Hz, WAKE_INTERVAL_S);
/* Initialize BURTC. */
if (! (RMU_RSTCAUSE_EM4WURST & reset_cause)) {
printf("Initializing BURTC\n");
BURTC->FREEZE = BURTC_FREEZE_REGFREEZE;
BURTC->LPMODE = BURTC_LPMODE_LPMODE_DISABLE;
BURTC->CTRL = burtc_ctrl /* CLKSEL + PRESC */
| BURTC_CTRL_RSTEN
| BURTC_CTRL_MODE_EM4EN
;
BURTC->COMP0 = WAKE_INTERVAL_S * lfa_Hz;
BURTC->IEN = BURTC_IF_COMP0;
BURTC->CTRL &= ~BURTC_CTRL_RSTEN;
BURTC->FREEZE = 0;
} else {
while (BURTC_SYNCBUSY_COMP0 & BURTC->SYNCBUSY) {
}
BURTC->COMP0 += WAKE_INTERVAL_S * lfa_Hz;
}
BURTC->IFC = BURTC_IFC_COMP0;
NVIC_EnableIRQ(BURTC_IRQn);
printf("BURTC CTRL %lx IEN %lx\n", BURTC->CTRL, BURTC->IEN);
(void)iBSPACMperiphUARTflush(hBSPACMdefaultUART, eBSPACMperiphUARTfifoState_TX);
while (1) {
static const sBSPACMperiphUARTconfiguration cfg = { .speed_baud = 0 };
printf("Sleeping in mode %u, %lu to %lu rtc_if %x or %lx\n", sleep_mode, BURTC->CNT, BURTC->COMP0, burtc_if, BURTC->IF);
BSPACM_CORE_DISABLE_INTERRUPT();
do {
(void)iBSPACMperiphUARTflush(hBSPACMdefaultUART, eBSPACMperiphUARTfifoState_TX);
hBSPACMperiphUARTconfigure(hBSPACMdefaultUART, 0);
switch (sleep_mode) {
case 0:
while (! (BURTC_IF_COMP0 & BURTC->IF)) {
}
++sleep_mode;
break;
case 1:
EMU_EnterEM1();
++sleep_mode;
break;
case 2:
EMU_EnterEM2(true);
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
if (cmuSelect_ULFRCO == CMU_ClockSelectGet(cmuClock_LFA)) {
++sleep_mode;
} else {
sleep_mode = 0;
}
break;
case 3:
EMU_EnterEM3(true);
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
if (cmuSelect_ULFRCO == CMU_ClockSelectGet(cmuClock_LFA)) {
++sleep_mode;
} else {
sleep_mode = 0;
}
break;
case 4:
EMU_EnterEM4();
sleep_mode = 0;
break;
}
} while (0);
BSPACM_CORE_ENABLE_INTERRUPT();
hBSPACMperiphUARTconfigure(hBSPACMdefaultUART, &cfg);
while (BURTC_SYNCBUSY_COMP0 & BURTC->SYNCBUSY) {
}
BURTC->COMP0 += WAKE_INTERVAL_S * lfa_Hz;
/* Giant Gecko
* Source EM0 EM1 EM2 EM3 EM4
* ULFRCO 2.5m 1.1m 622n 622n 450n
*/
}
}