static void ep93xx_gpio_update_int_params(unsigned port)
{
BUG_ON(port > 2);
__raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
__raw_writeb(gpio_int_type2[port],
EP93XX_GPIO_REG(int_type2_register_offset[port]));
__raw_writeb(gpio_int_type1[port],
EP93XX_GPIO_REG(int_type1_register_offset[port]));
__raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
EP93XX_GPIO_REG(int_en_register_offset[port]));
}
static void ep93xx_gpio_irq_ack(struct irq_data *d)
{
int line = irq_to_gpio(d->irq);
int port = line >> 3;
int port_mask = 1 << (line & 7);
if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
gpio_int_type2[port] ^= port_mask; /* switch edge direction */
ep93xx_gpio_update_int_params(port);
}
writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
}
static void ep93xx_gpio_int_debounce(unsigned int irq, bool enable)
{
int line = irq_to_gpio(irq);
int port = line >> 3;
int port_mask = 1 << (line & 7);
if (enable)
gpio_int_debounce[port] |= port_mask;
else
gpio_int_debounce[port] &= ~port_mask;
writeb(gpio_int_debounce[port],
EP93XX_GPIO_REG(int_debounce_register_offset[port]));
}
static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
{
int line = irq_to_gpio(d->irq);
int port = line >> 3;
int port_mask = 1 << (line & 7);
if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
gpio_int_type2[port] ^= port_mask;
gpio_int_unmasked[port] &= ~port_mask;
ep93xx_gpio_update_int_params(port);
__raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
}
