/******************************************************************************
* mvEthernetComplexPreInit
*
* DESCRIPTION:
* Perform basic setup that is needed before configuring the eth-complex
* registers.
*
* INPUT:
* ethCompCfg - Ethernet complex configuration.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_OK on success,
* MV_ERROR otherwise.
*******************************************************************************/
static MV_STATUS mvEthernetComplexPreInit(MV_U32 ethCompCfg)
{
MV_U32 reg, port;
/* Disable Polling mode. */
MV_REG_BIT_RESET(ETH_UNIT_CONTROL_REG(0), BIT1);
MV_REG_BIT_RESET(ETH_UNIT_CONTROL_REG(1), BIT1);
/* Set PHY address for MAC ports to 8 & 9 accordingly. */
/* The MAC Phy addresses need to be set before we enable the internal
** PHY / switch.
*/
if (ethCompCfg & (ESC_OPT_RGMIIA_MAC0 | ESC_OPT_RGMIIB_MAC0 | ESC_OPT_MAC0_2_SW_P4)) {
port = 0;
reg = MV_REG_READ(ETH_PHY_ADDR_REG(port));
reg &= ~ETH_PHY_ADDR_MASK;
reg |= mvBoardPhyAddrGet(port);
MV_REG_WRITE(ETH_PHY_ADDR_REG(port), reg);
}
MV_REG_WRITE(ETH_PHY_ADDR_REG(1), 0x9);
if (ethCompCfg & (ESC_OPT_RGMIIA_MAC1 | ESC_OPT_MAC1_2_SW_P5 | ESC_OPT_GEPHY_MAC1)) {
port = 1;
reg = MV_REG_READ(ETH_PHY_ADDR_REG(port));
reg &= ~ETH_PHY_ADDR_MASK;
reg |= mvBoardPhyAddrGet(port);
MV_REG_WRITE(ETH_PHY_ADDR_REG(port), reg);
}
return MV_OK;
}
/******************************************************************************
* mv_eth_tool_get_regs
* Description:
* ethtool get registers array
* INPUT:
* netdev Network device structure pointer
* regs registers information
* OUTPUT
* p registers array
* RETURN:
* None
*
*******************************************************************************/
void mv_eth_tool_get_regs(struct net_device *netdev,
struct ethtool_regs *regs, void *p)
{
struct eth_port *priv = MV_ETH_PRIV(netdev);
uint32_t *regs_buff = p;
memset(p, 0, MV_ETH_TOOL_REGS_LEN * sizeof(uint32_t));
regs->version = mvCtrlModelRevGet();
/* ETH port registers */
regs_buff[0] = MV_REG_READ(ETH_PORT_STATUS_REG(priv->port));
regs_buff[1] = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(priv->port));
regs_buff[2] = MV_REG_READ(ETH_PORT_CONFIG_REG(priv->port));
regs_buff[3] = MV_REG_READ(ETH_PORT_CONFIG_EXTEND_REG(priv->port));
regs_buff[4] = MV_REG_READ(ETH_SDMA_CONFIG_REG(priv->port));
/* regs_buff[5] = MV_REG_READ(ETH_TX_FIFO_URGENT_THRESH_REG(priv->port)); */
regs_buff[6] = MV_REG_READ(ETH_RX_QUEUE_COMMAND_REG(priv->port));
/* regs_buff[7] = MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(priv->port)); */
regs_buff[8] = MV_REG_READ(ETH_INTR_CAUSE_REG(priv->port));
regs_buff[9] = MV_REG_READ(ETH_INTR_CAUSE_EXT_REG(priv->port));
regs_buff[10] = MV_REG_READ(ETH_INTR_MASK_REG(priv->port));
regs_buff[11] = MV_REG_READ(ETH_INTR_MASK_EXT_REG(priv->port));
/* ETH Unit registers */
regs_buff[16] = MV_REG_READ(ETH_PHY_ADDR_REG(priv->port));
regs_buff[17] = MV_REG_READ(ETH_UNIT_INTR_CAUSE_REG(priv->port));
regs_buff[18] = MV_REG_READ(ETH_UNIT_INTR_MASK_REG(priv->port));
regs_buff[19] = MV_REG_READ(ETH_UNIT_ERROR_ADDR_REG(priv->port));
regs_buff[20] = MV_REG_READ(ETH_UNIT_INT_ADDR_ERROR_REG(priv->port));
}
/*******************************************************************************
* mvEthE1116PhyBasicInit -
*
* DESCRIPTION:
* Do a basic Init to the Phy , including reset
*
* INPUT:
* ethPortNum - Ethernet port number
*
* OUTPUT:
* None.
*
* RETURN: None
*
*******************************************************************************/
MV_VOID mvEthE1116PhyBasicInit(MV_U32 ethPortNum)
{
MV_U16 reg;
/* Set phy address */
MV_REG_WRITE(ETH_PHY_ADDR_REG(ethPortNum), mvBoardPhyAddrGet(ethPortNum));
/* Leds link and activity*/
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0x3);
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),16,®);
reg &= ~0xf;
reg |= 0x1;
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),16,reg);
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0x0);
/* Set RGMII delay */
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,2);
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),21,®);
reg |= (BIT5 | BIT4);
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),21,reg);
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0);
/* reset the phy */
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),0,®);
reg |= BIT15;
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),0,reg);
}
MV_VOID mvEth1121PhyBasicInit(MV_U32 port)
{
MV_U16 value;
MV_U16 phyAddr = mvBoardPhyAddrGet(port);
MV_REG_WRITE(ETH_PHY_ADDR_REG(port), phyAddr);
/* Change page select to 2 */
value = 2;
mvEthPhyRegWrite(phyAddr, 22, value);
mvOsDelay(10);
/* Set RGMII rx delay */
mvEthPhyRegRead(phyAddr, 21, &value);
value |= BIT5;
mvEthPhyRegWrite(phyAddr, 21, value);
mvOsDelay(10);
/* Change page select to 0 */
value = 0;
mvEthPhyRegWrite(phyAddr, 22, value);
mvOsDelay(10);
/* reset the phy */
mvEthPhyRegRead(phyAddr, 0, &value);
value |= BIT15;
mvEthPhyRegWrite(phyAddr, 0, value);
mvOsDelay(10);
}
/*******************************************************************************
* mvEthE1310PhyBasicInit -
*
* DESCRIPTION:
* Do a basic Init to the Phy , including reset
*
* INPUT:
* ethPortNum - Ethernet port number
*
* OUTPUT:
* None.
*
* RETURN: None
*
*******************************************************************************/
MV_VOID mvEthE1310PhyBasicInit(MV_U32 ethPortNum)
{
MV_U16 reg;
/* Set phy address */
MV_REG_WRITE(ETH_PHY_ADDR_REG(ethPortNum), mvBoardPhyAddrGet(ethPortNum));
/* Leds link and activity*/
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0x3);
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),16,®);
reg &= ~0xf;
reg |= 0x11;
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),16,reg);
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,0x0);
}
/*******************************************************************************
* mvEthE3016PhyBasicInit -
*
* DESCRIPTION:
* Do a basic Init to the Phy , including reset
*
* INPUT:
* ethPortNum - Ethernet port number
*
* OUTPUT:
* None.
*
* RETURN: None
*
*******************************************************************************/
MV_VOID mvEthE3016PhyBasicInit(MV_U32 ethPortNum)
{
MV_U16 reg;
/* Set phy address */
MV_REG_WRITE(ETH_PHY_ADDR_REG(ethPortNum), mvBoardPhyAddrGet(ethPortNum));
/* Leds link and activity*/
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),22,®);
reg &= ~0xf;
reg |= 0xa;
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),22,reg);
/* Set RGMII (RX) delay and copper mode */
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),28,®);
reg &= ~(BIT3 | BIT10 | BIT11);
reg |= (BIT10);
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),28,reg);
/* reset the phy */
mvEthPhyRegRead(mvBoardPhyAddrGet(ethPortNum),0,®);
reg |= BIT15;
mvEthPhyRegWrite(mvBoardPhyAddrGet(ethPortNum),0,reg);
}
/*******************************************************************************
* mvEth1145PhyInit - Initialize MARVELL 1145 Phy
*
* DESCRIPTION:
*
* INPUT:
* phyAddr - Phy address.
*
* OUTPUT:
* None.
*
* RETURN:
* None.
*
*******************************************************************************/
MV_VOID mvEth1145PhyBasicInit(MV_U32 port)
{
MV_U16 value;
/* Set phy address for each port */
MV_REG_WRITE(ETH_PHY_ADDR_REG(port), mvBoardPhyAddrGet(port));
/* Set Link1000 output pin to be link indication, set Tx output pin to be activity */
mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x18, ETH_PHY_LED_ACT_LNK_DV);
mvOsDelay(10);
/* Add delay to RGMII Tx and Rx */
mvEthPhyRegRead(mvBoardPhyAddrGet(port), 0x14, &value);
mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x14,(value | BIT1 | BIT7));
mvOsDelay(10);
#if 0 /* Fix by yotam */
if (boardId != RD_78XX0_AMC_ID &&
boardId != RD_78XX0_H3C_ID) {
/* Set port 2 - Phy addr 9 to RGMII */
if (port == 2)
{
mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x1b, 0x808b);
mvOsDelay(10);
}
/* Set port 1 - Phy addr a to SGMII */
if (port == 1)
{
mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x1b, 0x8084);
mvOsDelay(10);
/* Reset Phy */
mvEthPhyRegRead( mvBoardPhyAddrGet(port), 0x00, &value);
mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x00, (value | BIT15));
mvOsDelay(10);
#if defined(SGMII_OUTBAND_AN)
/* Set port 1 - Phy addr A Page 1 */
mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x16, 0x1);
mvOsDelay(10);
/* Set port 1 - Phy addr A disable A.N. */
mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x0, 0x140);
mvOsDelay(10);
/* Set port 1 - Phy addr A reset */
mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x0, 0x8140);
mvOsDelay(10);
mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x16, 0x0);
mvOsDelay(10);
#endif
}
}
#endif
/* Set Phy TPVL to 0 */
mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x10, 0x60);
mvOsDelay(10);
/* Reset Phy */
mvEthPhyRegRead(mvBoardPhyAddrGet(port), 0x00, &value);
mvEthPhyRegWrite(mvBoardPhyAddrGet(port), 0x00, (value | BIT15));
mvOsDelay(10);
return;
}
