//-----------------------------------------------------------------------------
// Task Dispatcher hooks
// The following hooks are called by the task dispatcher.
//-----------------------------------------------------------------------------
void TD_Init(void) // Called once at startup
{
// Init i2c bus for eeprom ez upgrade
EZUSB_InitI2C();
//Rwuen = TRUE; // Enable remote-wakeup
// Initializations
Init_IOs();
// Init Serial Interface and MIDI I/O buffers
// TD_Resume();
Init_Variables();
Init_Serial_Ports();
// Enable endpoint 2 in, and endpoint 2 out
//IN07VAL = bmEP2; // Validate all EP's
// IN07VAL = bmEP1; // Validate all EP's
IN07VAL = USB_ITRS_EP_IN;
OUT07VAL = bmEP2;
// Enable double buffering on endpoint 2 in, and endpoint 2 out
// USBPAIR = 0x09;
// USBPAIR = 0x08; // pair out endpoint 2&3
USBPAIR = USB_PAIRED_EP; // pair out endpoint 2&3
// Arm Endpoint 2 out to receive data
EPIO[OUT2BUF_ID].bytes = 0;
}
void DSLogic_Init(void)
{
// CLKSPD[1:0]=10, for 48MHz operation
CPUCS = 0x12;
SYNCDELAY;
// Setup Endpoints
SYNCDELAY;
EP2CFG = 0xA0; // EP2OUT, bulk, size 512, 2x buffered
SYNCDELAY;
EP6CFG = 0xE0; // EP6IN, bulk, size 512, 2x buffered
SYNCDELAY;
// Reset FIFOs
FIFORESET = 0x80; // set NAKALL bit to NAK all transfers from host
SYNCDELAY;
FIFORESET = 0x02; // reset EP2 FIFO
SYNCDELAY;
FIFORESET = 0x06; // reset EP6 FIFO
SYNCDELAY;
FIFORESET = 0x00; // clear NAKALL bit to resume normal operation
SYNCDELAY;
// EP2 Configuration
EP2FIFOCFG = 0x00; // allow core to see zero to one transition of auto out bit
SYNCDELAY;
EP2FIFOCFG = 0x10; // auto out mode, disable PKTEND zero length send, word ops
SYNCDELAY;
EP2GPIFFLGSEL = 0x01; // For EP2OUT, GPIF uses Empty flag
SYNCDELAY;
// EP6 Configuration
EP6FIFOCFG = 0x08; // auto in mode, disable PKTEND zero length send, word ops
SYNCDELAY;
EP6AUTOINLENH = 0x02; // Auto-commit 512 (0x200) byte packets (due to AUTOIN = 1)
SYNCDELAY;
EP6AUTOINLENL = 0x00;
SYNCDELAY;
EP6GPIFFLGSEL = 0x02; // For EP6IN, Set the GPIF flag to 'full'
SYNCDELAY;
// PA1~PA0: LED; PA2: Sample Enable; PA3: Sample Clear
OEA = 0x0f;
IOA = 0x00;
// GPIF Wavedata Init
setup_gpif_waveforms( );
// I2C Interface Init
EZUSB_InitI2C();
}
void TD_Init(void) // Called once at startup
{
// set the CPU clock to 48MHz
CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1) ;
CPUCS = CPUCS & 0xFD ; // 1111_1101
// set the slave FIFO interface to 30MHz, slave fifo mode
IFCONFIG = 0xA3; // 1010_0011
// disable interrupts by the input pins and by timers and serial ports:
IE &= 0x00; // 0000_0000
// disable interrupt pins 4, 5 and 6
EIE &= 0xE3; // 1110_0011;
// Registers which require a synchronization delay, see section 15.14
// FIFORESET FIFOPINPOLAR
// INPKTEND OUTPKTEND
// EPxBCH:L REVCTL
// GPIFTCB3 GPIFTCB2
// GPIFTCB1 GPIFTCB0
// EPxFIFOPFH:L EPxAUTOINLENH:L
// EPxFIFOCFG EPxGPIFFLGSEL
// PINFLAGSxx EPxFIFOIRQ
// EPxFIFOIE GPIFIRQ
// GPIFIE GPIFADRH:L
// UDMACRCH:L EPxGPIFTRIG
// GPIFTRIG
//enable Port C and port E
SYNCDELAY;
PORTCCFG = 0x00;
SYNCDELAY;
PORTACFG = 0x00; // do not use interrupts 0 and 1
SYNCDELAY;
PORTECFG = 0x00;
OEC = 0x0D; // 0000_1101 // JTAG, timestampMode, timestampTick, timestampMaster, resetTimestamp
OEE = 0xFE; // 1111_1110 configure only bit 0 (BitOut) as input
OEA = 0x88; // PA3: NotResetCPLD ; PA7 LED
// hold CPLD in reset and configure
// TimestampCounter to 1 us Tick (0): 0000_0000
IOC = 0x00;
IOA = 0x00;
IOE= 0x20; //set BiasClock high
EP1OUTCFG = 0x00; // EP1OUT disabled
SYNCDELAY;
EP1INCFG = 0xA0; // EP1IN enabled, bulk
SYNCDELAY;
EP2CFG = 0x00; // EP2 disabled
SYNCDELAY;
EP4CFG = 0x00; // EP4 disabled
SYNCDELAY;
EP6CFG = 0xE0; // EP6 enabled, in bulk, quad buffered
SYNCDELAY;
EP8CFG = 0x00; // EP8 disabled
SYNCDELAY;
REVCTL= 0x03;
EP6AUTOINLENH=0x02;
EP6AUTOINLENL=0x00;
SYNCDELAY;
EP6FIFOCFG = 0x09 ; //0000_1001
//set FIFO flag configuration: FlagB: EP6 full, flagC and D unused
SYNCDELAY;
PINFLAGSAB = 0xE8; // 1110_1000
// initialize variables
operationMode=0;
cycleCounter=0;
LED=1; // turn on to start
biasInit(); // init biasgen ports and pins
EZUSB_InitI2C(); // init I2C to enable EEPROM read and write
// IOE|=arrayReset; // un-reset all the pixels
IT0=1; // make INT0# edge-sensitive
EX0=0; // disable INT0# (this interrupt was used to signal to the host to reset WrapAdd)
IT1=1; // INT1# edge-sensitve
EX1=0; // disable INT1#
//startMonitor();
}
void TD_Init(void) // Called once at startup
{
// set the CPU clock to 48MHz
//CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1) ;
CPUCS = 0x12 ; // 1_0010 : CLKSP1:0=10, cpu clockspeed 48MHz, drive CLKOUT output pin 100 which clocks CPLD
/*
(from raphael berner: the clocking is as follows:
the fx2 clockes the CPLD by the CLKOUT pin (pin 100), and the CPLD clocks
the fifointerface on IFCLK, so in the firmware you should select external
clocksource in the FX2 for the slave FIFO clock source.
*/
IOC = 0x00;
IOA = 0x00;
IOE= 0x00; // set port output default values - enable them as outputs next
OEA = 0x8b; // 1000_1011. PA7 LED, PA3: nResetCPLD, PA1: runCPLD, PA0: tsReset
// port B is used as FD7-0 for 8 bit FIFO interface to CPLD
OEC = 0x0F; // now are cochlea and offchip DAC controls, before was 0000_1101 // JTAG, timestampMode, timestampTick, timestampMaster, resetTimestamp
OED = 0xFF; // all bit addressable outputs, all WORDWIDE=0 so port d should be enabled
OEE = 0x7F; // all outputs except scansync which is input, byte addressable
// set the slave FIFO interface to 30MHz, slave fifo mode
// select slave FIFO mode with with FIFO clock source as external clock (from CPLD).
// if the CPLD is not programmed there will not be any FIFO clock!
// if there is no IFCLK then the port D pins are never enabled as outputs.
// start with internal clock, switch to external CPLD clock source at end of TD_Init
SYNCDELAY;
IFCONFIG = 0xA3; // 0000_0011 // external clock, 30MHz, don't drive clock IFCLKOE, slave FIFO mode
SYNCDELAY; // may not be needed
// disable interrupts by the input pins and by timers and serial ports. timer2 scanner interrupt enabled when needed from vendor request.
IE &= 0x00; // 0000_0000
// disable interrupt pins 4, 5 and 6
EIE &= 0xE3; // 1110_0011;
// Registers which require a synchronization delay, see section 15.14
// FIFORESET FIFOPINPOLAR
// INPKTEND OUTPKTEND
// EPxBCH:L REVCTL
// GPIFTCB3 GPIFTCB2
// GPIFTCB1 GPIFTCB0
// EPxFIFOPFH:L EPxAUTOINLENH:L
// EPxFIFOCFG EPxGPIFFLGSEL
// PINFLAGSxx EPxFIFOIRQ
// EPxFIFOIE GPIFIRQ
// GPIFIE GPIFADRH:L
// UDMACRCH:L EPxGPIFTRIG
// GPIFTRIG
//disable all ports A,C,E alternate functions
SYNCDELAY;
PORTCCFG = 0x00;
SYNCDELAY;
PORTACFG = 0x00; // do not use interrupts 0 and 1
SYNCDELAY;
PORTECFG = 0x00;
EP1OUTCFG = 0x00; // EP1OUT disabled
SYNCDELAY;
EP1INCFG = 0xA0; // 1010 0000 VALID+Bulk EP1IN enabled, bulk
SYNCDELAY;
EP2CFG = 0x00; // EP2 disabled
SYNCDELAY;
EP4CFG = 0x00; // EP4 disabled
SYNCDELAY;
EP6CFG = 0xE0; // EP6 enabled, in bulk, quad buffered
SYNCDELAY;
EP8CFG = 0x00; // EP8 disabled
SYNCDELAY;
REVCTL= 0x03;
SYNCDELAY;
FIFORESET = 0x80;
SYNCDELAY;
FIFORESET = 0x06;
SYNCDELAY;
FIFORESET = 0x00;
SYNCDELAY;
EP6AUTOINLENH=0x02;
SYNCDELAY;
EP6AUTOINLENL=0x00;
SYNCDELAY;
EP6FIFOCFG = 0x08 ; //0000_1000, autoin=1, wordwide=0 to automatically commit packets and make this an 8 bit interface to FD
SYNCDELAY;
EP2FIFOCFG = 0x00 ; // wordwide=0
SYNCDELAY;
EP4FIFOCFG = 0x00 ;
SYNCDELAY;
EP8FIFOCFG = 0x00 ;
//set FIFO flag configuration: FlagB: EP6 full, flagC and D unused
SYNCDELAY;
PINFLAGSAB = 0xE8; // 1110_1000
SYNCDELAY;
cycleCounter=0;
// missedEvents=0xFFFFFFFF; // one interrupt is generated at startup, maybe some cpld registers start in high state
LED=1; // turn on LED
clock=1; bitIn=0; latch=0; powerDown=0; // init biasgen ports and pins
EZUSB_InitI2C(); // init I2C to enable EEPROM read and write
JTAGinit=TRUE;
IT0=1; // make INT0# edge-sensitive
EX0=0; // do not enable INT0#
IT1=1; // INT1# edge-sensitve
EX1=0; // do not enable INT1#
// timer2 init for scanner clocking in continuous mode
T2CON=0x00; // 0000 0100 timer2 control, set to 16 bit with autoreload, timer stopped
RCAP2L=0x00; // timer 2 low register loaded from vendor request.
RCAP2H=0xFF; // starting reload values, counter counts up to 0xFFFF from these and generates interrupt when count rolls to 0
ET2=0; // disable interrupt to start
/* // not using now writing initial bias values
for (i=0;i<NUM_BIAS_BYTES;i++)
{
spiwritebyte(biasBytes[i]);
}
latchNewBiases();
*/
toggleVReset();
// now switch to external IFCLK for FIFOs
// SYNCDELAY; // may not be needed
// IFCONFIG = 0x23; // 0010_0011 // extenal clock, slave fifo mode
// SYNCDELAY; // may not be needed
initDAC();
}