C++ (Cpp) FMC_BUSY_WAIT 예제들

예제 #1

파일: board.c 프로젝트: Salmista-94/u-boot

void start_ram(void)
{
	if (!dram_initialized)
		return;

	/*
	 * Precharge according to chip requirement, page 12.
	 */

	STM32_SDRAM_FMC->sdcmr = FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE;
	FMC_BUSY_WAIT();


	STM32_SDRAM_FMC->sdcmr = FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL;
	FMC_BUSY_WAIT();

	udelay(60);
}

예제 #2

파일: board.c 프로젝트: Salmista-94/u-boot

void stop_ram(void)
{
	if (!dram_initialized)
		return;

	STM32_SDRAM_FMC->sdcmr = FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_SELFREFRESH;

	FMC_BUSY_WAIT();
}

예제 #3

파일: stm32f429-discovery.c 프로젝트: CheezeCake/edison-u-boot

int dram_init(void)
{
	u32 freq;
	int rv;

	rv = fmc_setup_gpio();
	if (rv)
		return rv;

	setbits_le32(&STM32_RCC->ahb3enr, STM32_RCC_ENR_FMC);

	/*
	 * Get frequency for NS2CLK calculation.
	 */
	freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV;

	writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT
		| SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT
		| SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT,
		&STM32_SDRAM_FMC->sdcr1);

	writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT
		| SDRAM_CAS << FMC_SDCR_CAS_SHIFT
		| SDRAM_NB << FMC_SDCR_NB_SHIFT
		| SDRAM_MWID << FMC_SDCR_MWID_SHIFT
		| SDRAM_NR << FMC_SDCR_NR_SHIFT
		| SDRAM_NC << FMC_SDCR_NC_SHIFT
		| SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT
		| SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT,
		&STM32_SDRAM_FMC->sdcr2);

	writel(SDRAM_TRP << FMC_SDTR_TRP_SHIFT
		| SDRAM_TRC << FMC_SDTR_TRC_SHIFT,
		&STM32_SDRAM_FMC->sdtr1);

	writel(SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT
		| SDRAM_TRP << FMC_SDTR_TRP_SHIFT
		| SDRAM_TWR << FMC_SDTR_TWR_SHIFT
		| SDRAM_TRC << FMC_SDTR_TRC_SHIFT
		| SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT
		| SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT
		| SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT,
		&STM32_SDRAM_FMC->sdtr2);

	writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_START_CLOCK,
	       &STM32_SDRAM_FMC->sdcmr);

	udelay(200);	/* 200 us delay, page 10, "Power-Up" */
	FMC_BUSY_WAIT();

	writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_PRECHARGE,
	       &STM32_SDRAM_FMC->sdcmr);

	udelay(100);
	FMC_BUSY_WAIT();

	writel((FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_AUTOREFRESH
		| 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr);

	udelay(100);
	FMC_BUSY_WAIT();

	writel(FMC_SDCMR_BANK_2 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
		| SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT)
		<< FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
		&STM32_SDRAM_FMC->sdcmr);

	udelay(100);

	FMC_BUSY_WAIT();

	writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_NORMAL,
	       &STM32_SDRAM_FMC->sdcmr);

	FMC_BUSY_WAIT();

	/* Refresh timer */
	writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr);

	/*
	 * Fill in global info with description of SRAM configuration
	 */
	gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
	gd->bd->bi_dram[0].size  = CONFIG_SYS_RAM_SIZE;

	gd->ram_size = CONFIG_SYS_RAM_SIZE;

	return rv;
}

예제 #4

파일: board.c 프로젝트: Salmista-94/u-boot

int dram_init(void)
{
	u32 freq;
	int rv;

	/*
	 * Enable FMC interface clock
	 */
	STM32_RCC->ahb3enr |= STM32_RCC_ENR_FMC;

	/*
	 * Get frequency for NS2CLK calculation.
	 */
	freq = clock_get(CLOCK_HCLK) / CONFIG_SYS_RAM_FREQ_DIV;

	STM32_SDRAM_FMC->sdcr1 = (
		CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT |
		SDRAM_CAS << FMC_SDCR_CAS_SHIFT |
		SDRAM_NB << FMC_SDCR_NB_SHIFT |
		SDRAM_MWID << FMC_SDCR_MWID_SHIFT |
		SDRAM_NR << FMC_SDCR_NR_SHIFT |
		SDRAM_NC << FMC_SDCR_NC_SHIFT |
		0 << FMC_SDCR_RPIPE_SHIFT |
		1 << FMC_SDCR_RBURST_SHIFT
	);

	STM32_SDRAM_FMC->sdtr1 = (
		SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT |
		SDRAM_TRP << FMC_SDTR_TRP_SHIFT |
		SDRAM_TWR << FMC_SDTR_TWR_SHIFT |
		SDRAM_TRC << FMC_SDTR_TRC_SHIFT |
		SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT |
		SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT |
		SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT
	);

	STM32_SDRAM_FMC->sdcmr = FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK;

	udelay(200);	/* 200 us delay, page 10, "Power-Up" */
	FMC_BUSY_WAIT();

	STM32_SDRAM_FMC->sdcmr = FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE;

	udelay(100);
	FMC_BUSY_WAIT();

	STM32_SDRAM_FMC->sdcmr = (
		FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH |
		7 << FMC_SDCMR_NRFS_SHIFT
	);

	udelay(100);
	FMC_BUSY_WAIT();


#define SDRAM_MODE_BL_SHIFT		0
#define SDRAM_MODE_CAS_SHIFT		4

#define SDRAM_MODE_BL			0
#define SDRAM_MODE_CAS			SDRAM_CAS

	STM32_SDRAM_FMC->sdcmr = FMC_SDCMR_BANK_1 |
	(
		SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT |
		SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT
	) << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE;

	udelay(100);

	FMC_BUSY_WAIT();

	STM32_SDRAM_FMC->sdcmr = FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL;

	FMC_BUSY_WAIT();

	/* Refresh timer */
	STM32_SDRAM_FMC->sdrtr = SDRAM_TREF;

	/*
	 * Fill in global info with description of SRAM configuration
	 */
	gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
	gd->bd->bi_dram[0].size  = CONFIG_SYS_RAM_SIZE;

	rv = 0;

	dram_initialized = 1;

	return rv;
}

예제 #5

파일: stm32_sdram.c 프로젝트: Noltari/u-boot

int stm32_sdram_init(struct udevice *dev)
{
	struct stm32_sdram_params *params = dev_get_platdata(dev);
	struct stm32_sdram_control *control;
	struct stm32_sdram_timing *timing;
	struct stm32_fmc_regs *regs = params->base;
	enum stm32_fmc_bank target_bank;
	u32 ctb; /* SDCMR register: Command Target Bank */
	u32 ref_count;
	u8 i;

	/* disable the FMC controller */
	if (params->family == STM32H7_FMC)
		clrbits_le32(&regs->bcr1, FMC_BCR1_FMCEN);

	for (i = 0; i < params->no_sdram_banks; i++) {
		control = params->bank_params[i].sdram_control;
		timing = params->bank_params[i].sdram_timing;
		target_bank = params->bank_params[i].target_bank;
		ref_count = params->bank_params[i].sdram_ref_count;

		writel(control->sdclk << FMC_SDCR_SDCLK_SHIFT
			| control->cas_latency << FMC_SDCR_CAS_SHIFT
			| control->no_banks << FMC_SDCR_NB_SHIFT
			| control->memory_width << FMC_SDCR_MWID_SHIFT
			| control->no_rows << FMC_SDCR_NR_SHIFT
			| control->no_columns << FMC_SDCR_NC_SHIFT
			| control->rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT
			| control->rd_burst << FMC_SDCR_RBURST_SHIFT,
			&regs->sdcr1);

		if (target_bank == SDRAM_BANK2)
			writel(control->cas_latency << FMC_SDCR_CAS_SHIFT
				| control->no_banks << FMC_SDCR_NB_SHIFT
				| control->memory_width << FMC_SDCR_MWID_SHIFT
				| control->no_rows << FMC_SDCR_NR_SHIFT
				| control->no_columns << FMC_SDCR_NC_SHIFT,
				&regs->sdcr2);

		writel(timing->trcd << FMC_SDTR_TRCD_SHIFT
			| timing->trp << FMC_SDTR_TRP_SHIFT
			| timing->twr << FMC_SDTR_TWR_SHIFT
			| timing->trc << FMC_SDTR_TRC_SHIFT
			| timing->tras << FMC_SDTR_TRAS_SHIFT
			| timing->txsr << FMC_SDTR_TXSR_SHIFT
			| timing->tmrd << FMC_SDTR_TMRD_SHIFT,
			&regs->sdtr1);

		if (target_bank == SDRAM_BANK2)
			writel(timing->trcd << FMC_SDTR_TRCD_SHIFT
				| timing->trp << FMC_SDTR_TRP_SHIFT
				| timing->twr << FMC_SDTR_TWR_SHIFT
				| timing->trc << FMC_SDTR_TRC_SHIFT
				| timing->tras << FMC_SDTR_TRAS_SHIFT
				| timing->txsr << FMC_SDTR_TXSR_SHIFT
				| timing->tmrd << FMC_SDTR_TMRD_SHIFT,
				&regs->sdtr2);

		if (target_bank == SDRAM_BANK1)
			ctb = FMC_SDCMR_BANK_1;
		else
			ctb = FMC_SDCMR_BANK_2;

		writel(ctb | FMC_SDCMR_MODE_START_CLOCK, &regs->sdcmr);
		udelay(200);	/* 200 us delay, page 10, "Power-Up" */
		FMC_BUSY_WAIT(regs);

		writel(ctb | FMC_SDCMR_MODE_PRECHARGE, &regs->sdcmr);
		udelay(100);
		FMC_BUSY_WAIT(regs);

		writel((ctb | FMC_SDCMR_MODE_AUTOREFRESH | 7 << FMC_SDCMR_NRFS_SHIFT),
		       &regs->sdcmr);
		udelay(100);
		FMC_BUSY_WAIT(regs);

		writel(ctb | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
		       | control->cas_latency << SDRAM_MODE_CAS_SHIFT)
		       << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
		       &regs->sdcmr);
		udelay(100);
		FMC_BUSY_WAIT(regs);

		writel(ctb | FMC_SDCMR_MODE_NORMAL, &regs->sdcmr);
		FMC_BUSY_WAIT(regs);

		/* Refresh timer */
		writel(ref_count << 1, &regs->sdrtr);
	}

	/* enable the FMC controller */
	if (params->family == STM32H7_FMC)
		setbits_le32(&regs->bcr1, FMC_BCR1_FMCEN);

	return 0;
}