void GBMemoryReset(struct GB* gb) {
if (gb->memory.wram) {
mappedMemoryFree(gb->memory.wram, GB_SIZE_WORKING_RAM);
}
gb->memory.wram = anonymousMemoryMap(GB_SIZE_WORKING_RAM);
if (gb->model >= GB_MODEL_CGB) {
uint32_t* base = (uint32_t*) gb->memory.wram;
size_t i;
uint32_t pattern = 0;
for (i = 0; i < GB_SIZE_WORKING_RAM / 4; i += 4) {
if ((i & 0x1FF) == 0) {
pattern = ~pattern;
}
base[i + 0] = pattern;
base[i + 1] = pattern;
base[i + 2] = ~pattern;
base[i + 3] = ~pattern;
}
}
GBMemorySwitchWramBank(&gb->memory, 1);
gb->memory.romBank = &gb->memory.rom[GB_SIZE_CART_BANK0];
gb->memory.currentBank = 1;
gb->memory.sramCurrentBank = 0;
gb->memory.ime = false;
gb->memory.ie = 0;
gb->memory.dmaNext = INT_MAX;
gb->memory.dmaRemaining = 0;
gb->memory.dmaSource = 0;
gb->memory.dmaDest = 0;
gb->memory.hdmaNext = INT_MAX;
gb->memory.hdmaRemaining = 0;
gb->memory.hdmaSource = 0;
gb->memory.hdmaDest = 0;
gb->memory.isHdma = false;
gb->memory.sramAccess = false;
gb->memory.rtcAccess = false;
gb->memory.activeRtcReg = 0;
gb->memory.rtcLatched = false;
memset(&gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
memset(&gb->memory.hram, 0, sizeof(gb->memory.hram));
memset(&gb->memory.mbcState, 0, sizeof(gb->memory.mbcState));
GBMBCInit(gb);
gb->memory.sramBank = gb->memory.sram;
if (!gb->memory.wram) {
GBMemoryDeinit(gb);
}
}
void GBIOWrite(struct GB* gb, unsigned address, uint8_t value) {
switch (address) {
case REG_DIV:
GBTimerDivReset(&gb->timer);
return;
case REG_NR10:
if (gb->audio.enable) {
GBAudioWriteNR10(&gb->audio, value);
} else {
value = 0;
}
break;
case REG_NR11:
if (gb->audio.enable) {
GBAudioWriteNR11(&gb->audio, value);
} else {
if (gb->audio.style == GB_AUDIO_DMG) {
GBAudioWriteNR11(&gb->audio, value & _registerMask[REG_NR11]);
}
value = 0;
}
break;
case REG_NR12:
if (gb->audio.enable) {
GBAudioWriteNR12(&gb->audio, value);
} else {
value = 0;
}
break;
case REG_NR13:
if (gb->audio.enable) {
GBAudioWriteNR13(&gb->audio, value);
} else {
value = 0;
}
break;
case REG_NR14:
if (gb->audio.enable) {
GBAudioWriteNR14(&gb->audio, value);
} else {
value = 0;
}
break;
case REG_NR21:
if (gb->audio.enable) {
GBAudioWriteNR21(&gb->audio, value);
} else {
if (gb->audio.style == GB_AUDIO_DMG) {
GBAudioWriteNR21(&gb->audio, value & _registerMask[REG_NR21]);
}
value = 0;
}
break;
case REG_NR22:
if (gb->audio.enable) {
GBAudioWriteNR22(&gb->audio, value);
} else {
value = 0;
}
break;
case REG_NR23:
if (gb->audio.enable) {
GBAudioWriteNR23(&gb->audio, value);
} else {
value = 0;
}
break;
case REG_NR24:
if (gb->audio.enable) {
GBAudioWriteNR24(&gb->audio, value);
} else {
value = 0;
}
break;
case REG_NR30:
if (gb->audio.enable) {
GBAudioWriteNR30(&gb->audio, value);
} else {
value = 0;
}
break;
case REG_NR31:
if (gb->audio.enable || gb->audio.style == GB_AUDIO_DMG) {
GBAudioWriteNR31(&gb->audio, value);
} else {
value = 0;
}
break;
case REG_NR32:
if (gb->audio.enable) {
GBAudioWriteNR32(&gb->audio, value);
} else {
value = 0;
}
break;
case REG_NR33:
if (gb->audio.enable) {
GBAudioWriteNR33(&gb->audio, value);
} else {
value = 0;
}
break;
case REG_NR34:
if (gb->audio.enable) {
GBAudioWriteNR34(&gb->audio, value);
} else {
value = 0;
}
break;
case REG_NR41:
if (gb->audio.enable || gb->audio.style == GB_AUDIO_DMG) {
GBAudioWriteNR41(&gb->audio, value);
} else {
value = 0;
}
break;
case REG_NR42:
if (gb->audio.enable) {
GBAudioWriteNR42(&gb->audio, value);
} else {
value = 0;
}
break;
case REG_NR43:
if (gb->audio.enable) {
GBAudioWriteNR43(&gb->audio, value);
} else {
value = 0;
}
break;
case REG_NR44:
if (gb->audio.enable) {
GBAudioWriteNR44(&gb->audio, value);
} else {
value = 0;
}
break;
case REG_NR50:
if (gb->audio.enable) {
GBAudioWriteNR50(&gb->audio, value);
} else {
value = 0;
}
break;
case REG_NR51:
if (gb->audio.enable) {
GBAudioWriteNR51(&gb->audio, value);
} else {
value = 0;
}
break;
case REG_NR52:
GBAudioWriteNR52(&gb->audio, value);
value &= 0x80;
value |= gb->memory.io[REG_NR52] & 0x0F;
break;
case REG_WAVE_0:
case REG_WAVE_1:
case REG_WAVE_2:
case REG_WAVE_3:
case REG_WAVE_4:
case REG_WAVE_5:
case REG_WAVE_6:
case REG_WAVE_7:
case REG_WAVE_8:
case REG_WAVE_9:
case REG_WAVE_A:
case REG_WAVE_B:
case REG_WAVE_C:
case REG_WAVE_D:
case REG_WAVE_E:
case REG_WAVE_F:
if (!gb->audio.playingCh3 || gb->audio.style != GB_AUDIO_DMG) {
gb->audio.ch3.wavedata8[address - REG_WAVE_0] = value;
} else if(gb->audio.ch3.readable) {
gb->audio.ch3.wavedata8[gb->audio.ch3.window >> 1] = value;
}
break;
case REG_JOYP:
case REG_TIMA:
case REG_TMA:
case REG_LYC:
// Handled transparently by the registers
break;
case REG_TAC:
value = GBTimerUpdateTAC(&gb->timer, value);
break;
case REG_IF:
gb->memory.io[REG_IF] = value | 0xE0;
GBUpdateIRQs(gb);
return;
case REG_LCDC:
// TODO: handle GBC differences
value = gb->video.renderer->writeVideoRegister(gb->video.renderer, address, value);
GBVideoWriteLCDC(&gb->video, value);
break;
case REG_DMA:
GBMemoryDMA(gb, value << 8);
break;
case REG_SCY:
case REG_SCX:
case REG_WY:
case REG_WX:
GBVideoProcessDots(&gb->video);
value = gb->video.renderer->writeVideoRegister(gb->video.renderer, address, value);
break;
case REG_BGP:
case REG_OBP0:
case REG_OBP1:
GBVideoProcessDots(&gb->video);
GBVideoWritePalette(&gb->video, address, value);
break;
case REG_STAT:
GBVideoWriteSTAT(&gb->video, value);
break;
case REG_IE:
gb->memory.ie = value;
GBUpdateIRQs(gb);
return;
default:
if (gb->model >= GB_MODEL_CGB) {
switch (address) {
case REG_KEY1:
value &= 0x1;
value |= gb->memory.io[address] & 0x80;
break;
case REG_VBK:
GBVideoSwitchBank(&gb->video, value);
break;
case REG_HDMA1:
case REG_HDMA2:
case REG_HDMA3:
case REG_HDMA4:
// Handled transparently by the registers
break;
case REG_HDMA5:
GBMemoryWriteHDMA5(gb, value);
value &= 0x7F;
break;
case REG_BCPS:
gb->video.bcpIndex = value & 0x3F;
gb->video.bcpIncrement = value & 0x80;
gb->memory.io[REG_BCPD] = gb->video.palette[gb->video.bcpIndex >> 1] >> (8 * (gb->video.bcpIndex & 1));
break;
case REG_BCPD:
GBVideoProcessDots(&gb->video);
GBVideoWritePalette(&gb->video, address, value);
break;
case REG_OCPS:
gb->video.ocpIndex = value & 0x3F;
gb->video.ocpIncrement = value & 0x80;
gb->memory.io[REG_OCPD] = gb->video.palette[8 * 4 + (gb->video.ocpIndex >> 1)] >> (8 * (gb->video.ocpIndex & 1));
break;
case REG_OCPD:
GBVideoProcessDots(&gb->video);
GBVideoWritePalette(&gb->video, address, value);
break;
case REG_SVBK:
GBMemorySwitchWramBank(&gb->memory, value);
value = gb->memory.wramCurrentBank;
break;
default:
goto failed;
}
goto success;
}
failed:
mLOG(GB_IO, STUB, "Writing to unknown register FF%02X:%02X", address, value);
if (address >= GB_SIZE_IO) {
return;
}
break;
}
void GBMemoryDeserialize(struct GB* gb, const struct GBSerializedState* state) {
struct GBMemory* memory = &gb->memory;
memcpy(memory->wram, state->wram, GB_SIZE_WORKING_RAM);
memcpy(memory->hram, state->hram, GB_SIZE_HRAM);
LOAD_16LE(memory->currentBank, 0, &state->memory.currentBank);
memory->wramCurrentBank = state->memory.wramCurrentBank;
memory->sramCurrentBank = state->memory.sramCurrentBank;
GBMBCSwitchBank(gb, memory->currentBank);
GBMemorySwitchWramBank(memory, memory->wramCurrentBank);
GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
LOAD_16LE(memory->dmaSource, 0, &state->memory.dmaSource);
LOAD_16LE(memory->dmaDest, 0, &state->memory.dmaDest);
LOAD_16LE(memory->hdmaSource, 0, &state->memory.hdmaSource);
LOAD_16LE(memory->hdmaDest, 0, &state->memory.hdmaDest);
LOAD_16LE(memory->hdmaRemaining, 0, &state->memory.hdmaRemaining);
memory->dmaRemaining = state->memory.dmaRemaining;
memcpy(memory->rtcRegs, state->memory.rtcRegs, sizeof(state->memory.rtcRegs));
uint32_t when;
LOAD_32LE(when, 0, &state->memory.dmaNext);
if (memory->dmaRemaining) {
mTimingSchedule(&gb->timing, &memory->dmaEvent, when);
}
LOAD_32LE(when, 0, &state->memory.hdmaNext);
if (memory->hdmaRemaining) {
mTimingSchedule(&gb->timing, &memory->hdmaEvent, when);
}
GBSerializedMemoryFlags flags;
LOAD_16LE(flags, 0, &state->memory.flags);
memory->sramAccess = GBSerializedMemoryFlagsGetSramAccess(flags);
memory->rtcAccess = GBSerializedMemoryFlagsGetRtcAccess(flags);
memory->rtcLatched = GBSerializedMemoryFlagsGetRtcLatched(flags);
memory->ime = GBSerializedMemoryFlagsGetIme(flags);
memory->isHdma = GBSerializedMemoryFlagsGetIsHdma(flags);
memory->activeRtcReg = GBSerializedMemoryFlagsGetActiveRtcReg(flags);
switch (memory->mbcType) {
case GB_MBC1:
memory->mbcState.mbc1.mode = state->memory.mbc1.mode;
memory->mbcState.mbc1.multicartStride = state->memory.mbc1.multicartStride;
if (memory->mbcState.mbc1.mode) {
GBMBCSwitchBank0(gb, memory->currentBank >> memory->mbcState.mbc1.multicartStride);
}
break;
case GB_MBC3_RTC:
LOAD_64LE(gb->memory.rtcLastLatch, 0, &state->memory.rtc.lastLatch);
break;
case GB_MBC7:
memory->mbcState.mbc7.state = state->memory.mbc7.state;
memory->mbcState.mbc7.eeprom = state->memory.mbc7.eeprom;
memory->mbcState.mbc7.address = state->memory.mbc7.address & 0x7F;
memory->mbcState.mbc7.access = state->memory.mbc7.access;
memory->mbcState.mbc7.latch = state->memory.mbc7.latch;
memory->mbcState.mbc7.srBits = state->memory.mbc7.srBits;
LOAD_16LE(memory->mbcState.mbc7.sr, 0, &state->memory.mbc7.sr);
LOAD_32LE(memory->mbcState.mbc7.writable, 0, &state->memory.mbc7.writable);
break;
default:
break;
}
void GBMemoryReset(struct GB* gb) {
if (gb->memory.wram) {
mappedMemoryFree(gb->memory.wram, GB_SIZE_WORKING_RAM);
}
gb->memory.wram = anonymousMemoryMap(GB_SIZE_WORKING_RAM);
if (gb->model >= GB_MODEL_CGB) {
uint32_t* base = (uint32_t*) gb->memory.wram;
size_t i;
uint32_t pattern = 0;
for (i = 0; i < GB_SIZE_WORKING_RAM / 4; i += 4) {
if ((i & 0x1FF) == 0) {
pattern = ~pattern;
}
base[i + 0] = pattern;
base[i + 1] = pattern;
base[i + 2] = ~pattern;
base[i + 3] = ~pattern;
}
}
GBMemorySwitchWramBank(&gb->memory, 1);
gb->memory.romBank = &gb->memory.rom[GB_SIZE_CART_BANK0];
gb->memory.currentBank = 1;
gb->memory.sramCurrentBank = 0;
gb->memory.ime = false;
gb->memory.ie = 0;
gb->memory.dmaRemaining = 0;
gb->memory.dmaSource = 0;
gb->memory.dmaDest = 0;
gb->memory.hdmaRemaining = 0;
gb->memory.hdmaSource = 0;
gb->memory.hdmaDest = 0;
gb->memory.isHdma = false;
gb->memory.dmaEvent.context = gb;
gb->memory.dmaEvent.name = "GB DMA";
gb->memory.dmaEvent.callback = _GBMemoryDMAService;
gb->memory.dmaEvent.priority = 0x40;
gb->memory.hdmaEvent.context = gb;
gb->memory.hdmaEvent.name = "GB HDMA";
gb->memory.hdmaEvent.callback = _GBMemoryHDMAService;
gb->memory.hdmaEvent.priority = 0x41;
memset(&gb->memory.hram, 0, sizeof(gb->memory.hram));
switch (gb->memory.mbcType) {
case GB_MBC1:
gb->memory.mbcState.mbc1.mode = 0;
break;
default:
memset(&gb->memory.mbcState, 0, sizeof(gb->memory.mbcState));
}
GBMBCInit(gb);
gb->memory.sramBank = gb->memory.sram;
if (!gb->memory.wram) {
GBMemoryDeinit(gb);
}
}
