/** * Prints various local APIC registers of interest to the console. */ void lapic_dump(void) { char buf[128]; printk(KERN_DEBUG "LOCAL APIC DUMP (LOGICAL CPU #%d):\n", this_cpu); /* * Lead off with the important stuff... */ printk(KERN_DEBUG " ID: 0x%08x (id=%d)\n", apic_read(APIC_ID), GET_APIC_ID(apic_read(APIC_ID)) ); printk(KERN_DEBUG " VER: 0x%08x (version=0x%x, max_lvt=%d)\n", apic_read(APIC_LVR), GET_APIC_VERSION(apic_read(APIC_LVR)), GET_APIC_MAXLVT(apic_read(APIC_LVR)) ); printk(KERN_DEBUG " ESR: 0x%08x (Error Status Reg, non-zero is bad)\n", apic_read(APIC_ESR) ); printk(KERN_DEBUG " SVR: 0x%08x (Spurious vector=%d, %s)\n", apic_read(APIC_SPIV), apic_read(APIC_SPIV) & APIC_VECTOR_MASK, (apic_read(APIC_SPIV) & APIC_SPIV_APIC_ENABLED) ? "APIC IS ENABLED" : "APIC IS DISABLED" ); /* * Local Vector Table */ printk(KERN_DEBUG " Local Vector Table Entries:\n"); printk(KERN_DEBUG " LVT[0] Timer: 0x%08x (%s)\n", apic_read(APIC_LVTT), lvt_stringify(apic_read(APIC_LVTT), buf) ); printk(KERN_DEBUG " LVT[1] Thermal: 0x%08x (%s)\n", apic_read(APIC_LVTTHMR), lvt_stringify(apic_read(APIC_LVTTHMR), buf) ); printk(KERN_DEBUG " LVT[2] Perf Cnt: 0x%08x (%s)\n", apic_read(APIC_LVTPC), lvt_stringify(apic_read(APIC_LVTPC), buf) ); printk(KERN_DEBUG " LVT[3] LINT0 Pin: 0x%08x (%s)\n", apic_read(APIC_LVT0), lvt_stringify(apic_read(APIC_LVT0), buf) ); printk(KERN_DEBUG " LVT[4] LINT1 Pin: 0x%08x (%s)\n", apic_read(APIC_LVT1), lvt_stringify(apic_read(APIC_LVT1), buf) ); printk(KERN_DEBUG " LVT[5] Error: 0x%08x (%s)\n", apic_read(APIC_LVTERR), lvt_stringify(apic_read(APIC_LVTERR), buf) ); /* * APIC timer configuration registers */ printk(KERN_DEBUG " Local APIC Timer:\n"); printk(KERN_DEBUG " DCR (Divide Config Reg): 0x%08x\n", apic_read(APIC_TDCR) ); printk(KERN_DEBUG " ICT (Initial Count Reg): 0x%08x\n", apic_read(APIC_TMICT) ); printk(KERN_DEBUG " CCT (Current Count Reg): 0x%08x\n", apic_read(APIC_TMCCT) ); /* * Logical APIC addressing mode registers */ printk(KERN_DEBUG " Logical Addressing Mode Information:\n"); printk(KERN_DEBUG " LDR (Logical Dest Reg): 0x%08x (id=%d)\n", apic_read(APIC_LDR), GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)) ); printk(KERN_DEBUG " DFR (Dest Format Reg): 0x%08x (%s)\n", apic_read(APIC_DFR), (apic_read(APIC_DFR) == APIC_DFR_FLAT) ? "FLAT" : "CLUSTER" ); /* * Task/processor/arbitration priority registers */ printk(KERN_DEBUG " Task/Processor/Arbitration Priorities:\n"); printk(KERN_DEBUG " TPR (Task Priority Reg): 0x%08x\n", apic_read(APIC_TASKPRI) ); printk(KERN_DEBUG " PPR (Processor Priority Reg): 0x%08x\n", apic_read(APIC_PROCPRI) ); printk(KERN_DEBUG " APR (Arbitration Priority Reg): 0x%08x\n", apic_read(APIC_ARBPRI) ); }
static void apic_dump (struct apic_dev * apic) { char buf[128]; APIC_DEBUG("DUMP (LOGICAL CPU #%u):\n", my_cpu_id()); APIC_DEBUG( " ID: 0x%08x (id=%d)\n", apic_read(apic, APIC_REG_ID), APIC_GET_ID(apic_read(apic, APIC_REG_ID)) ); APIC_DEBUG( " VER: 0x%08x (version=0x%x, max_lvt=%d)\n", apic_read(apic, APIC_REG_LVR), APIC_LVR_VER(apic_read(apic, APIC_REG_LVR)), APIC_LVR_MAX(apic_read(apic, APIC_REG_LVR)) ); APIC_DEBUG( " BASE ADDR: %p\n", apic->base_addr ); if (nk_is_amd() && amd_has_ext_lvt(apic)) { APIC_DEBUG( " EXT (AMD-only): 0x%08x (Ext LVT Count=%u, Ext APIC ID=%u, Specific EOI=%u, Int Enable Reg=%u)\n", apic_read(apic, APIC_REG_EXFR), APIC_EXFR_GET_LVT(apic_read(apic, APIC_REG_EXFR)), APIC_EXFR_GET_XAIDC(apic_read(apic, APIC_REG_EXFR)), APIC_EXFR_GET_SNIC(apic_read(apic, APIC_REG_EXFR)), APIC_EXFR_GET_INC(apic_read(apic, APIC_REG_EXFR)) ); int i; for (i = 0; i < APIC_EXFR_GET_LVT(apic_read(apic, APIC_REG_EXFR)); i++) { APIC_DEBUG( " EXT-LVT[%u]: 0x%08x (%s)\n", i, apic_read(apic, APIC_REG_EXTLVT(i)), lvt_stringify(apic_read(apic, APIC_REG_EXTLVT(i)), buf) ); } } APIC_DEBUG( " ESR: 0x%08x (Error Status Reg, non-zero is bad)\n", apic_read(apic, APIC_REG_ESR) ); APIC_DEBUG( " SVR: 0x%08x (Spurious vector=%d, %s, %s)\n", apic_read(apic, APIC_REG_SPIV), apic_read(apic, APIC_REG_SPIV) & APIC_SPIV_VEC_MASK, (apic_read(apic, APIC_REG_SPIV) & APIC_SPIV_SW_ENABLE) ? "APIC IS ENABLED" : "APIC IS DISABLED", (apic_read(apic, APIC_REG_SPIV) & APIC_SPIV_CORE_FOCUS) ? "Core Focusing Disabled" : "Core Focusing Enabled" ); /* * Local Vector Table */ APIC_DEBUG(" Local Vector Table Entries:\n"); char * timer_mode; if (apic_read(apic, APIC_REG_LVTT) & APIC_TIMER_PERIODIC) { timer_mode = "Periodic"; } else if (apic_read(apic, APIC_REG_LVTT) & APIC_TIMER_TSCDLINE) { timer_mode = "TSC-Deadline"; } else { timer_mode = "One-shot"; } APIC_DEBUG(" LVT[0] Timer: 0x%08x (mode=%s, %s)\n", apic_read(apic, APIC_REG_LVTT), timer_mode, lvt_stringify(apic_read(apic, APIC_REG_LVTT), buf) ); APIC_DEBUG(" LVT[1] Thermal: 0x%08x (%s)\n", apic_read(apic, APIC_REG_LVTTHMR), lvt_stringify(apic_read(apic, APIC_REG_LVTTHMR), buf) ); APIC_DEBUG(" LVT[2] Perf Cnt: 0x%08x (%s)\n", apic_read(apic, APIC_REG_LVTPC), lvt_stringify(apic_read(apic, APIC_REG_LVTPC), buf) ); APIC_DEBUG(" LVT[3] LINT0 Pin: 0x%08x (%s)\n", apic_read(apic, APIC_REG_LVT0), lvt_stringify(apic_read(apic, APIC_REG_LVT0), buf) ); APIC_DEBUG(" LVT[4] LINT1 Pin: 0x%08x (%s)\n", apic_read(apic, APIC_REG_LVT1), lvt_stringify(apic_read(apic, APIC_REG_LVT1), buf) ); APIC_DEBUG(" LVT[5] Error: 0x%08x (%s)\n", apic_read(apic, APIC_REG_LVTERR), lvt_stringify(apic_read(apic, APIC_REG_LVTERR), buf) ); /* * APIC timer configuration registers */ APIC_DEBUG(" Local APIC Timer:\n"); APIC_DEBUG(" DCR (Divide Config Reg): 0x%08x\n", apic_read(apic, APIC_REG_TMDCR) ); APIC_DEBUG(" ICT (Initial Count Reg): 0x%08x\n", apic_read(apic, APIC_REG_TMICT) ); APIC_DEBUG(" CCT (Current Count Reg): 0x%08x\n", apic_read(apic, APIC_REG_TMCCT) ); /* * Logical APIC addressing mode registers */ APIC_DEBUG(" Logical Addressing Mode Information:\n"); APIC_DEBUG(" LDR (Logical Dest Reg): 0x%08x (id=%d)\n", apic_read(apic, APIC_REG_LDR), GET_APIC_LOGICAL_ID(apic_read(apic, APIC_REG_LDR)) ); APIC_DEBUG(" DFR (Dest Format Reg): 0x%08x (%s)\n", apic_read(apic, APIC_REG_DFR), (apic_read(apic, APIC_REG_DFR) == APIC_DFR_FLAT) ? "FLAT" : "CLUSTER" ); /* * Task/processor/arbitration priority registers */ APIC_DEBUG(" Task/Processor/Arbitration Priorities:\n"); APIC_DEBUG(" TPR (Task Priority Reg): 0x%08x\n", apic_read(apic, APIC_REG_TPR) ); APIC_DEBUG(" PPR (Processor Priority Reg): 0x%08x\n", apic_read(apic, APIC_REG_PPR) ); APIC_DEBUG(" APR (Arbitration Priority Reg): 0x%08x\n", apic_read(apic, APIC_REG_APR) ); /* * ISR/IRR */ APIC_DEBUG(" IRR/ISR:\n"); APIC_DEBUG(" IRR (Interrupt Request Reg): 0x%08x\n", apic_read(apic, APIC_GET_IRR(0))); APIC_DEBUG(" 0x%08x\n", apic_read(apic, APIC_GET_IRR(1))); APIC_DEBUG(" 0x%08x\n", apic_read(apic, APIC_GET_IRR(2))); APIC_DEBUG(" 0x%08x\n", apic_read(apic, APIC_GET_IRR(3))); APIC_DEBUG(" 0x%08x\n", apic_read(apic, APIC_GET_IRR(4))); APIC_DEBUG(" 0x%08x\n", apic_read(apic, APIC_GET_IRR(5))); APIC_DEBUG(" 0x%08x\n", apic_read(apic, APIC_GET_IRR(6))); APIC_DEBUG(" 0x%08x\n", apic_read(apic, APIC_GET_IRR(7))); APIC_DEBUG(" ISR (In-Service Reg): 0x%08x\n", apic_read(apic, APIC_GET_ISR(0))); APIC_DEBUG(" 0x%08x\n", apic_read(apic, APIC_GET_ISR(1))); APIC_DEBUG(" 0x%08x\n", apic_read(apic, APIC_GET_ISR(2))); APIC_DEBUG(" 0x%08x\n", apic_read(apic, APIC_GET_ISR(3))); APIC_DEBUG(" 0x%08x\n", apic_read(apic, APIC_GET_ISR(4))); APIC_DEBUG(" 0x%08x\n", apic_read(apic, APIC_GET_ISR(5))); APIC_DEBUG(" 0x%08x\n", apic_read(apic, APIC_GET_ISR(6))); APIC_DEBUG(" 0x%08x\n", apic_read(apic, APIC_GET_ISR(7))); }