/************************************************************************
*
* Function Name : PFlashSetProtection.c
* Description : This function sets the P-Flash protection to the
* intended protection status
* Arguments : PFLASH_SSD_CONFIG, UINT32
* Return Value : UINT32
*
*************************************************************************/
UINT32 PFlashSetProtection(PFLASH_SSD_CONFIG pSSDConfig, \
UINT32 protectStatus)
{
UINT8 reg0, reg1, reg2, reg3;
UINT32 ret;
ret = FTFx_OK;
reg0 = GET_BIT_24_31(protectStatus);
reg1 = GET_BIT_16_23(protectStatus);
reg2 = GET_BIT_8_15(protectStatus);
reg3 = GET_BIT_0_7(protectStatus);
REG_WRITE(pSSDConfig->ftfxRegBase + FTFx_SSD_FPROT0_OFFSET, reg0);
REG_WRITE(pSSDConfig->ftfxRegBase + FTFx_SSD_FPROT1_OFFSET, reg1);
REG_WRITE(pSSDConfig->ftfxRegBase + FTFx_SSD_FPROT2_OFFSET, reg2);
REG_WRITE(pSSDConfig->ftfxRegBase + FTFx_SSD_FPROT3_OFFSET, reg3);
/* Read the value of FPPROT registers */
if ((REG_READ(pSSDConfig->ftfxRegBase + FTFx_SSD_FPROT0_OFFSET) != reg0) ||\
(REG_READ(pSSDConfig->ftfxRegBase + FTFx_SSD_FPROT1_OFFSET) != reg1) ||\
(REG_READ(pSSDConfig->ftfxRegBase + FTFx_SSD_FPROT2_OFFSET) != reg2) ||\
(REG_READ(pSSDConfig->ftfxRegBase + FTFx_SSD_FPROT3_OFFSET) != reg3))
{
ret = FTFx_ERR_CHANGEPROT;
}
/* Enter Debug state if enabled */
if (TRUE == (pSSDConfig->DebugEnable))
{
ENTER_DEBUG_MODE;
}
return(ret);
}
uint32_t SIZE_OPTIMIZATION PFlashSwapCtl(PFLASH_SSD_CONFIG pSSDConfig,uint32_t addr, uint8_t swapcmd,uint8_t* pCurrentSwapMode, \
uint8_t* pCurrentSwapBlockStatus, \
uint8_t* pNextSwapBlockStatus, \
pFLASHCOMMANDSEQUENCE pFlashCommandSequence)
{
uint32_t ret; /* Return code variable */
uint32_t temp; /* temporary variable */
addr = WORD2BYTE(addr - pSSDConfig->PFlashBase);
/* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register. Write 1 to clear*/
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET;
REG_WRITE(temp, FTFx_SSD_FSTAT_ERROR_BITS);
/* passing parameter to the command */
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB0_OFFSET;
REG_WRITE(temp, FTFx_PFLASH_SWAP);
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB1_OFFSET;
REG_WRITE(temp, GET_BIT_16_23(addr));
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB2_OFFSET;
REG_WRITE(temp, GET_BIT_8_15(addr));
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB3_OFFSET;
REG_WRITE(temp, GET_BIT_0_7(addr));
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB4_OFFSET;
REG_WRITE(temp, swapcmd);
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB5_OFFSET;
REG_WRITE(temp, 0xFFU);
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB6_OFFSET;
REG_WRITE(temp, 0xFFU);
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB7_OFFSET;
REG_WRITE(temp, 0xFFU);
/* calling flash command sequence function to execute the command */
ret = pFlashCommandSequence(pSSDConfig);
if (FTFx_OK == ret)
{
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB5_OFFSET;
*pCurrentSwapMode = REG_READ(temp);
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB6_OFFSET;
*pCurrentSwapBlockStatus = REG_READ(temp);
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB7_OFFSET;
*pNextSwapBlockStatus = REG_READ(temp);
}
#if C90TFS_ENABLE_DEBUG
/* Enter Debug state if enabled */
if (TRUE == (pSSDConfig->DebugEnable))
{
ENTER_DEBUG_MODE;
}
#endif
return (ret);
}
uint32_t SIZE_OPTIMIZATION PFlashSetProtection(PFLASH_SSD_CONFIG pSSDConfig, \
uint32_t protectStatus)
{
uint32_t ret = FTFx_OK;
uint32_t addr;
uint32_t temp0, temp1, temp2, temp3;
uint8_t reg0, reg1, reg2, reg3;
reg0 = GET_BIT_24_31(protectStatus);
reg1 = GET_BIT_16_23(protectStatus);
reg2 = GET_BIT_8_15(protectStatus);
reg3 = GET_BIT_0_7(protectStatus);
addr = pSSDConfig->ftfxRegBase + FTFx_SSD_FPROT0_OFFSET;
REG_WRITE(addr, reg0);
temp0 = REG_READ(addr);
addr = pSSDConfig->ftfxRegBase + FTFx_SSD_FPROT1_OFFSET;
REG_WRITE(addr, reg1);
temp1 = REG_READ(addr);
addr = pSSDConfig->ftfxRegBase + FTFx_SSD_FPROT2_OFFSET;
REG_WRITE(addr, reg2);
temp2 = REG_READ(addr);
addr = pSSDConfig->ftfxRegBase + FTFx_SSD_FPROT3_OFFSET;
REG_WRITE(addr, reg3);
temp3 = REG_READ(addr);
/* Read the value of FPPROT registers */
if ((temp0 != reg0) || (temp1 != reg1) || (temp2 != reg2) || (temp3 != reg3))
{
ret = FTFx_ERR_CHANGEPROT;
}
#if C90TFS_ENABLE_DEBUG
/* Enter Debug state if enabled */
if (TRUE == (pSSDConfig->DebugEnable))
{
ENTER_DEBUG_MODE;
}
#endif
return(ret);
}
uint32_t SIZE_OPTIMIZATION FlashVerifySection(PFLASH_SSD_CONFIG pSSDConfig, \
uint32_t dest, \
uint16_t number, \
uint8_t marginLevel, \
pFLASHCOMMANDSEQUENCE pFlashCommandSequence)
{
uint32_t ret = FTFx_OK; /* return code variable */
uint32_t temp;
/* convert to byte address */
dest = WORD2BYTE(dest);
/* check if the destination is aligned or not */
#if (DEBLOCK_SIZE)
temp = WORD2BYTE(pSSDConfig->DFlashBlockBase);
if((dest >= temp) && (dest < (temp + pSSDConfig->DFlashBlockSize)))
{
dest = dest - temp + 0x800000U;
}
else
#endif
{
temp = WORD2BYTE(pSSDConfig->PFlashBlockBase);
if((dest >= temp) && (dest < (temp + pSSDConfig->PFlashBlockSize)))
{
dest -= temp;
}
else
{
ret = FTFx_ERR_ACCERR;
}
}
if(FTFx_OK == ret)
{
/* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register. Write 1 to clear*/
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET;
REG_WRITE(temp, FTFx_SSD_FSTAT_ERROR_BITS);
/* passing parameter to the command */
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB0_OFFSET;
REG_WRITE(temp, FTFx_VERIFY_SECTION);
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB1_OFFSET;
REG_WRITE(temp, GET_BIT_16_23(dest));
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB2_OFFSET;
REG_WRITE(temp, GET_BIT_8_15(dest));
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB3_OFFSET;
REG_WRITE(temp, GET_BIT_0_7(dest));
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB4_OFFSET;
REG_WRITE(temp, GET_BIT_8_15(number));
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB5_OFFSET;
REG_WRITE(temp, GET_BIT_0_7(number));
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB6_OFFSET;
REG_WRITE(temp, marginLevel);
/* calling flash command sequence function to execute the command */
ret = pFlashCommandSequence(pSSDConfig);
}
#if C90TFS_ENABLE_DEBUG
/* Enter Debug state if enabled */
if (TRUE == (pSSDConfig->DebugEnable))
{
ENTER_DEBUG_MODE;
}
#endif
return(ret);
}
/****************************************************************************
*
* Function Name : FlashEraseSector
* Description : Perform erase operation on Flash
* Arguments : PFLASH_SSD_CONFIG, UINT32, UINT32, pFLASHCOMMANDSEQUENCE
* Return Value : UINT32
*
*****************************************************************************/
UINT32 FlashEraseSector(PFLASH_SSD_CONFIG pSSDConfig, \
UINT32 dest, \
UINT32 size, \
pFLASHCOMMANDSEQUENCE pFlashCommandSequence)
{
UINT32 ret; /* return code variable */
UINT32 sectorSize ,temp; /* size of one sector */
ret = FTFx_OK;
/* convert to byte address */
dest = WORD2BYTE(dest);
#if (DEBLOCK_SIZE)
temp = WORD2BYTE(pSSDConfig->DFlashBlockBase);
if((dest >= temp) && (dest < (temp + pSSDConfig->DFlashBlockSize)))
{
dest = dest - temp + 0x800000;
sectorSize = FTFx_DSECTOR_SIZE;
}
else
#endif
{
temp = WORD2BYTE(pSSDConfig->PFlashBlockBase);
if((dest >= temp) && (dest < (temp + pSSDConfig->PFlashBlockSize)))
{
dest -= temp;
sectorSize = FTFx_PSECTOR_SIZE;
}else{
ret = FTFx_ERR_ACCERR;
goto EXIT;
}
}
/* check if the size is sector alignment or not */
if(size & (sectorSize-1))
{
/* return an error code FTFx_ERR_SIZE */
ret = FTFx_ERR_SIZE;
goto EXIT;
}
while(size > 0)
{
/* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register. Write 1 to clear*/
REG_WRITE(pSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET,FTFx_SSD_FSTAT_ERROR_BITS);
/* passing parameter to the command */
REG_WRITE(pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB0_OFFSET, FTFx_ERASE_SECTOR);
REG_WRITE(pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB1_OFFSET, GET_BIT_16_23(dest));
REG_WRITE(pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB2_OFFSET, GET_BIT_8_15(dest));
REG_WRITE(pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB3_OFFSET, GET_BIT_0_7(dest));
/* calling flash command sequence function to execute the command */
ret = pFlashCommandSequence(pSSDConfig);
/* checking the success of command execution */
if(FTFx_OK != ret)
{
break;
}
else
{
/* update size and destination address */
size -= sectorSize;
dest += sectorSize;
}
}
EXIT:
/* Enter Debug state if enabled */
if (TRUE == (pSSDConfig->DebugEnable))
{
ENTER_DEBUG_MODE;
}
return(ret);
}
uint32_t SIZE_OPTIMIZATION FlashReadResource(PFLASH_SSD_CONFIG pSSDConfig, \
uint32_t dest, \
uint8_t* pDataArray, \
uint8_t resourceSelectCode, \
pFLASHCOMMANDSEQUENCE pFlashCommandSequence)
{
uint8_t i;
uint32_t ret = FTFx_OK; /* return code variable */
uint32_t temp;
/* convert to byte address */
dest = WORD2BYTE(dest);
/* check if the destination is aligned or not */
#if (DEBLOCK_SIZE)
temp = WORD2BYTE(pSSDConfig->DFlashBase);
if((dest >= temp) && (dest < (temp + pSSDConfig->DFlashSize)))
{
dest = dest - temp + 0x800000U;
}
else
#endif
{
temp = WORD2BYTE(pSSDConfig->PFlashBase);
if((dest >= temp) && (dest < (temp + pSSDConfig->PFlashSize)))
{
dest -= temp;
}
else
{
ret = FTFx_ERR_ACCERR;
}
}
if(ret == FTFx_OK)
{
/* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register. Write 1 to clear */
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET;
REG_WRITE(temp, FTFx_SSD_FSTAT_ERROR_BITS);
/* passing parameter to the command */
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB0_OFFSET;
REG_WRITE(temp, FTFx_READ_RESOURCE);
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB1_OFFSET;
REG_WRITE(temp, GET_BIT_16_23(dest));
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB2_OFFSET;
REG_WRITE(temp, GET_BIT_8_15(dest));
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB3_OFFSET;
REG_WRITE(temp, GET_BIT_0_7(dest));
temp = pSSDConfig->ftfxRegBase + RSRC_CODE_OFSSET;
REG_WRITE(temp, resourceSelectCode);
/* calling flash command sequence function to execute the command */
ret = pFlashCommandSequence(pSSDConfig);
if (FTFx_OK == ret)
{
/* Read the data from the FCCOB registers into the pDataArray */
for (i = 0x0U; i < PGM_SIZE_BYTE; i ++)
{
temp = pSSDConfig->ftfxRegBase + i + 0x08U;
pDataArray[i] = REG_READ(temp);
}
}
}
#if C90TFS_ENABLE_DEBUG
/* Enter Debug state if enabled */
if (TRUE == (pSSDConfig->DebugEnable))
{
ENTER_DEBUG_MODE;
}
#endif
return(ret);
}
uint32_t SIZE_OPTIMIZATION FlashProgramSection(PFLASH_SSD_CONFIG pSSDConfig, \
uint32_t dest, \
uint16_t number, \
pFLASHCOMMANDSEQUENCE pFlashCommandSequence)
{
uint32_t ret = FTFx_OK; /* return code variable */
uint32_t temp;
/* check RAMRDY bit of the flash configuration register */
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCNFG_OFFSET;
if(0x0U == (REG_BIT_GET(temp, FTFx_SSD_FCNFG_RAMRDY)))
{
/* return an error code FTFx_ERR_RAMRDY */
ret = FTFx_ERR_RAMRDY;
}
else
{
/* convert to byte address */
dest = WORD2BYTE(dest);
#if (DEBLOCK_SIZE)
temp = WORD2BYTE(pSSDConfig->DFlashBase);
if((dest >= temp) && (dest < (temp + pSSDConfig->DFlashSize)))
{
dest = dest - temp + 0x800000U;
}
else
#endif
{
temp = WORD2BYTE(pSSDConfig->PFlashBase);
if((dest >= temp) && (dest < (temp + pSSDConfig->PFlashSize)))
{
dest -= temp;
}
else
{
ret = FTFx_ERR_ACCERR;
}
}
if(ret == FTFx_OK)
{
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET;
REG_WRITE(temp, FTFx_SSD_FSTAT_ERROR_BITS);
/* passing parameter to command */
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB0_OFFSET;
REG_WRITE(temp, FTFx_PROGRAM_SECTION);
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB1_OFFSET;
REG_WRITE(temp, GET_BIT_16_23(dest));
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB2_OFFSET;
REG_WRITE(temp, GET_BIT_8_15(dest));
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB3_OFFSET;
REG_WRITE(temp, GET_BIT_0_7(dest));
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB4_OFFSET;
REG_WRITE(temp, GET_BIT_8_15(number));
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB5_OFFSET;
REG_WRITE(temp, GET_BIT_0_7(number));
/* calling flash command sequence function to execute the command */
ret = pFlashCommandSequence(pSSDConfig);
}
}
#if C90TFS_ENABLE_DEBUG
/* Enter Debug state if enabled */
if (TRUE == (pSSDConfig->DebugEnable))
{
ENTER_DEBUG_MODE;
}
#endif
return(ret);
}
