static PCADDR
fr500_check_insn_read_address (SIM_CPU *current_cpu, PCADDR address,
int align_mask)
{
if (address & align_mask)
{
frv_queue_mem_address_not_aligned_interrupt (current_cpu, address);
address &= ~align_mask;
}
if ((USI)address >= 0xfeff0600 && (USI)address <= 0xfeff7fff
|| (USI)address >= 0xfe800000 && (USI)address <= 0xfefeffff)
frv_queue_instruction_access_error_interrupt (current_cpu);
else if ((USI)address >= 0xfe004000 && (USI)address <= 0xfe3fffff
|| (USI)address >= 0xfe400000 && (USI)address <= 0xfe403fff
|| (USI)address >= 0xfe404000 && (USI)address <= 0xfe7fffff)
frv_queue_instruction_access_exception_interrupt (current_cpu);
else
{
USI hsr0 = GET_HSR0 ();
if (! GET_HSR0_RME (hsr0)
&& (USI)address >= 0xfe000000 && (USI)address <= 0xfe003fff)
frv_queue_instruction_access_exception_interrupt (current_cpu);
}
return address;
}
/* Determine whether the given address should be accessed without using
the cache. */
static int
non_cache_access (FRV_CACHE *cache, USI address)
{
int hsr0;
SIM_DESC sd;
SIM_CPU *current_cpu = cache->cpu;
sd = CPU_STATE (current_cpu);
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
case bfd_mach_fr450:
if (address >= 0xff000000
|| address >= 0xfe000000 && address <= 0xfeffffff)
return 1; /* non-cache access */
break;
case bfd_mach_fr550:
if (address >= 0xff000000
|| address >= 0xfeff0000 && address <= 0xfeffffff)
return 1; /* non-cache access */
if (cache == CPU_INSN_CACHE (current_cpu))
{
if (address >= 0xfe000000 && address <= 0xfe007fff)
return 1; /* non-cache access */
}
else if (address >= 0xfe400000 && address <= 0xfe407fff)
return 1; /* non-cache access */
break;
default:
if (address >= 0xff000000
|| address >= 0xfeff0000 && address <= 0xfeffffff)
return 1; /* non-cache access */
if (cache == CPU_INSN_CACHE (current_cpu))
{
if (address >= 0xfe000000 && address <= 0xfe003fff)
return 1; /* non-cache access */
}
else if (address >= 0xfe400000 && address <= 0xfe403fff)
return 1; /* non-cache access */
break;
}
hsr0 = GET_HSR0 ();
if (GET_HSR0_RME (hsr0))
return ram_access (cache, address);
return 0; /* cache-access */
}
static SI
fr550_check_readwrite_address (SIM_CPU *current_cpu, SI address, int align_mask)
{
/* No alignment restrictions on fr550 */
if ((USI)address >= 0xfe000000 && (USI)address <= 0xfe3fffff
|| (USI)address >= 0xfe408000 && (USI)address <= 0xfe7fffff)
frv_queue_data_access_exception_interrupt (current_cpu);
else
{
USI hsr0 = GET_HSR0 ();
if (! GET_HSR0_RME (hsr0)
&& (USI)address >= 0xfe400000 && (USI)address <= 0xfe407fff)
frv_queue_data_access_exception_interrupt (current_cpu);
}
return address;
}
static PCADDR
fr550_check_insn_read_address (SIM_CPU *current_cpu, PCADDR address,
int align_mask)
{
address &= ~align_mask;
if ((USI)address >= 0xfe800000 && (USI)address <= 0xfeffffff)
frv_queue_instruction_access_error_interrupt (current_cpu);
else if ((USI)address >= 0xfe008000 && (USI)address <= 0xfe7fffff)
frv_queue_instruction_access_exception_interrupt (current_cpu);
else
{
USI hsr0 = GET_HSR0 ();
if (! GET_HSR0_RME (hsr0)
&& (USI)address >= 0xfe000000 && (USI)address <= 0xfe007fff)
frv_queue_instruction_access_exception_interrupt (current_cpu);
}
return address;
}
