/**
* Initialize necessary allocated buffer lists for GMAC Driver to transfer data.
* Must be invoked after GMACD_Init() but before RX/TX start.
* Replace the deprecated GMACD_InitTransfer().
* \param pGmacd Pointer to GMAC Driver instance.
* \param pInit Pointer to sGmacInit.
* \param pInit Pointer to gmacQueList_t for different queue.
* \return GMACD_OK or GMACD_PARAM.
* \note If input address is not 8-byte aligned the address is automatically
* adjusted and the list size is reduced by one.
*/
uint8_t GMACD_InitTransfer(sGmacd *pGmacd, const sGmacInit *pInit,
gmacQueList_t queIdx)
{
Gmac *pHw = pGmacd->pHw;
uint8_t *pRxBuffer = pInit->pRxBuffer;
sGmacRxDescriptor *pRxD = pInit->pRxD;
uint16_t wRxBufferSize = pInit->wRxBufferSize;
uint16_t wRxSize = pInit->wRxSize;
uint8_t *pTxBuffer = pInit->pTxBuffer;
sGmacTxDescriptor *pTxD = pInit->pTxD;
uint16_t wTxBufferSize = pInit->wTxBufferSize;
uint16_t wTxSize = pInit->wTxSize;
fGmacdTransferCallback *pTxCb = pInit->pTxCb;
uint32_t dwDmaCfg;
if (wRxSize <= 1 || wTxSize <= 1 || pTxCb == NULL) return GMACD_PARAM;
if (!wRxBufferSize || wRxBufferSize > 16 * 1024 || wRxBufferSize & 0x3f)
return GMACD_PARAM;
if (!wTxBufferSize)
return GMACD_PARAM;
if (pInit->bIsGem) {
if (!queIdx) {
dwDmaCfg = (GMAC_DCFGR_DRBS(wRxBufferSize >> 6))
| GMAC_DCFGR_RXBMS(3) | GMAC_DCFGR_TXPBMS;
switch (pInit->bDmaBurstLength) {
case 16:
dwDmaCfg |= GMAC_DCFGR_FBLDO_INCR16;
break;
case 8:
dwDmaCfg |= GMAC_DCFGR_FBLDO_INCR8;
break;
case 4:
dwDmaCfg |= GMAC_DCFGR_FBLDO_INCR4;
break;
case 1:
dwDmaCfg |= GMAC_DCFGR_FBLDO_SINGLE;
break;
default:
return GMACD_PARAM;
}
} else
static void __MacInitialize(tagMacDriver *pDrive)
{
Gmac *pHw;
tagQueue *que;
u32 index;
u32 value;
pHw = pDrive->pHw;
GMAC_DEBUG("Mac Initialize start...\n\r");
//make it power on
PMC_EnablePeripheral(pDrive->bId);
//first,we must stop the device to receive or send
GMAC_NetworkControl(pHw, 0);
//disable all the interrupts
GMAC_DisableAllQueueIt(pHw, ~0u);
//do the stat clearing
GMAC_ClearStatistics(pHw);
/* Clear all status bits in the receive status register. */
GMAC_ClearRxStatus(pHw, GMAC_RSR_RXOVR | GMAC_RSR_REC
| GMAC_RSR_BNA |GMAC_RSR_HNO);
/* Clear all status bits in the transmit status register */
GMAC_ClearTxStatus(pHw, GMAC_TSR_UBR | GMAC_TSR_COL | GMAC_TSR_RLE
| GMAC_TSR_TXGO | GMAC_TSR_TFC | GMAC_TSR_TXCOMP
| GMAC_TSR_HRESP );
//here we begin to configure the mac device
for(index =0;index < CN_QUE_NUM;index ++)
{
que = &pDrive->queueList[CN_QUE_0];
GMAC_GetItStatus(pHw, index); //read for clear
/*initialize the bd*/
__MacBdSndInit(index);
__MacBdRcvInit(index);
/*set the dma configuration*/
if(index == CN_QUE_0)
{
value = (GMAC_DCFGR_DRBS(que->rcvbuflen >> 6) )
| GMAC_DCFGR_RXBMS(3) | GMAC_DCFGR_TXPBMS |GMAC_DCFGR_DDRP|GMAC_DCFGR_FBLDO_INCR4;
}
else
{
