int gpio_set_pullup(unsigned int pin, unsigned int pull) { unsigned int gpio_num = GPIO_NUM(pin); unsigned int bank = GPIO_BANK(gpio_num); unsigned int offset = gpio_num % 32; if (pmu == 0 || iomux == 0) { return -1; } if (pin < RK30_PIN0_PB4) { unsigned long *base = (unsigned long *) (pmu + PMU_GPIO0A_PULL + ((offset / 8) * 4)); offset = (offset % 8) * 2; unsigned long value = *base; value &= ~(0x03 << offset); value |= (0x03 << (16 + offset) | (pull << offset)); *base = value; } else { unsigned long *base = (unsigned long *) (iomux + GRF_GPIO0B_PULL - 4 + bank * 16 + ((offset / 8) * 4)); offset = (7 - (offset % 8)) * 2; unsigned long value = *base; value &= ~(0x03 << offset); value |= ((0x03 << (16 + offset)) | (pull << offset)); *base = value; } return 0; }
static int sunxi_gpio_set_value(struct udevice *dev, unsigned offset, int value) { struct sunxi_gpio_platdata *plat = dev_get_platdata(dev); u32 num = GPIO_NUM(offset); clrsetbits_le32(&plat->regs->dat, 1 << num, value ? (1 << num) : 0); return 0; }
static int sunxi_gpio_direction_output(struct udevice *dev, unsigned offset, int value) { struct sunxi_gpio_platdata *plat = dev_get_platdata(dev); u32 num = GPIO_NUM(offset); sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_OUTPUT); clrsetbits_le32(&plat->regs->dat, 1 << num, value ? (1 << num) : 0); return 0; }
static int sunxi_gpio_get_value(struct udevice *dev, unsigned offset) { struct sunxi_gpio_platdata *plat = dev_get_platdata(dev); u32 num = GPIO_NUM(offset); unsigned dat; dat = readl(&plat->regs->dat); dat >>= num; return dat & 0x1; }
static int sunxi_gpio_input(u32 pin) { u32 dat; u32 bank = GPIO_BANK(pin); u32 num = GPIO_NUM(pin); struct sunxi_gpio *pio = BANK_TO_GPIO(bank); dat = readl(&pio->dat); dat >>= num; return dat & 0x1; }
static int sunxi_gpio_input(u32 pin) { u32 dat; u32 bank = GPIO_BANK(pin); u32 num = GPIO_NUM(pin); struct sunxi_gpio *pio = &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank]; dat = readl(&pio->dat); dat >>= num; return dat & 0x1; }
int sunxi_gpio_input(unsigned int pin) { unsigned int dat; unsigned int bank = GPIO_BANK(pin); unsigned int num = GPIO_NUM(pin); if(SUNXI_PIO_BASE == 0) { return -1; } struct sunxi_gpio *pio =&((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank]; dat = *(&pio->dat); dat >>= num; return (dat & 0x1); }
int sunxi_gpio_output(unsigned int pin, unsigned int val) { unsigned int bank = GPIO_BANK(pin); unsigned int num = GPIO_NUM(pin); if(SUNXI_PIO_BASE == 0) { return -1; } struct sunxi_gpio *pio =&((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank]; if(val) *(&pio->dat) |= 1 << num; else *(&pio->dat) &= ~(1 << num); return 0; }
static int sunxi_gpio_output(u32 pin, u32 val) { u32 dat; u32 bank = GPIO_BANK(pin); u32 num = GPIO_NUM(pin); struct sunxi_gpio *pio = BANK_TO_GPIO(bank); dat = readl(&pio->dat); if (val) dat |= 0x1 << num; else dat &= ~(0x1 << num); writel(dat, &pio->dat); return 0; }
static int sunxi_gpio_output(u32 pin, u32 val) { u32 dat; u32 bank = GPIO_BANK(pin); u32 num = GPIO_NUM(pin); struct sunxi_gpio *pio = &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank]; dat = readl(&pio->dat); if (val) dat |= 0x1 << num; else dat &= ~(0x1 << num); writel(dat, &pio->dat); return 0; }
int gpio_set_cfgpin(unsigned int pin, unsigned int val) { unsigned int gpio_num = GPIO_NUM(pin); #if defined(RK3188) unsigned int bank = GPIO_BANK(gpio_num); unsigned int offset = GPIO_OFFSET(gpio_num); #elif defined(AM3352) unsigned int bank = GPIO_BANK(pin); unsigned long offset = 1 << gpio_num; #endif debug("PIN: %d\n", pin); debug("GPIO_NUM: %d\n", gpio_num); debug("GPIO_BANK: %d\n", bank); debug("OFFSET: 0x%08lx\n", offset); if (gpio[bank].gpio_pio_base == 0) { return -1; } struct gpio_reg *pio = ((struct gpio_reg *) gpio[bank].gpio_pio_base); debug("GPIO_OE: 0x%08lx\n", pio->gpio_oe); if (val == GPIO_INPUT) { #if defined(RK3188) pio->gpio_swport_ddr &= ~offset; #elif defined(AM3352) pio->gpio_oe |= offset; #endif } else { #if defined(RK3188) pio->gpio_swport_ddr |= offset; #elif defined(AM3352) pio->gpio_oe &= ~offset; #endif } debug("GPIO_OE: 0x%08lx\n", pio->gpio_oe); return 0; }
GpioState GpioPlateformImplementation::internalRead() { const int pinNum = SUNXI_GPD( _pin ); unsigned int dat; unsigned int bank = GPIO_BANK( pinNum ); unsigned int num = GPIO_NUM( pinNum ); if(s_sunxi_pio_base == 0) return undefined; struct sunxi_gpio *pio =&((struct sunxi_gpio_reg *) s_sunxi_pio_base )->gpio_bank[bank]; dat = *(&pio->dat); dat >>= num; return ( GpioState ) (dat & 0x1); }
/*static*/ void GpioPlateformImplementation::internalSetOutput( const int pin , const GpioState state ) { const int pinNum = SUNXI_GPD( pin ); unsigned int bank = GPIO_BANK( pinNum ); unsigned int num = GPIO_NUM( pinNum ); if( s_sunxi_pio_base == 0) { return ; } struct sunxi_gpio *pio =&((struct sunxi_gpio_reg *) s_sunxi_pio_base )->gpio_bank[bank]; if( state == high ) *(&pio->dat) |= 1 << num; else *(&pio->dat) &= ~(1 << num); }
int gpio_get_cfgpin(unsigned int pin) { unsigned int gpio_num = GPIO_NUM(pin); #if defined(RK3188) unsigned int bank = GPIO_BANK(gpio_num); unsigned int offset = GPIO_OFFSET(gpio_num); #elif defined(AM3352) unsigned int bank = GPIO_BANK(pin); unsigned int offset = 1 << gpio_num; #endif if (gpio[bank].gpio_pio_base == 0) { return -1; } struct gpio_reg *pio = ((struct gpio_reg *) gpio[bank].gpio_pio_base); #if defined(RK3188) return !!(pio->gpio_swport_ddr & offset); #elif defined(AM3352) return !!(pio->gpio_oe & offset); #endif }
int gpio_make_gpio(unsigned int pin) { unsigned int gpio_num = GPIO_NUM(pin); //23 unsigned int bank = GPIO_BANK(gpio_num); // 0 unsigned int offset = (gpio_num % 32) / 8; // 2 if (iomux == 0) { return -1; } //0x20008060 + bank*0x10 + 4*(gpio_num / 8) unsigned int *ptr = (unsigned int *) (iomux + GPIO_GRF_IOMUX + bank * 16 + 4 * offset); unsigned long value = *((unsigned long *) ptr) & ~(0x03 << 2 * (gpio_num % 8)); value |= 3 << (2 * (gpio_num % 8) + 16); *((unsigned long*) ptr) = value; return 0; }
int gpio_input(unsigned int pin) { unsigned int gpio_num = GPIO_NUM(pin); #if defined(RK3188) unsigned int bank = GPIO_BANK(gpio_num); unsigned int offset = GPIO_OFFSET(gpio_num); #elif defined(AM3352) unsigned int bank = GPIO_BANK(pin); unsigned int offset = 1 << gpio_num; #endif if (gpio[bank].gpio_pio_base == 0) { return -1; } struct gpio_reg *pio = ((struct gpio_reg *) gpio[bank].gpio_pio_base); #if defined(RK3188) return !!(pio->gpio_ext_port & offset); #elif defined(AM3352) return !!(pio->gpio_datain & offset); #endif }
int gpio_output(unsigned int pin, unsigned int val) { unsigned int gpio_num = GPIO_NUM(pin); #if defined(RK3188) unsigned int bank = GPIO_BANK(gpio_num); unsigned int offset = GPIO_OFFSET(gpio_num); #elif defined(AM3352) unsigned int bank = GPIO_BANK(pin); unsigned int offset = 1 << gpio_num; #endif if (gpio[bank].gpio_pio_base == 0) { return -1; } struct gpio_reg *pio = ((struct gpio_reg *) gpio[bank].gpio_pio_base); debug("GPIO_DATAOUT: 0x%08lx\n", pio->gpio_dataout); if (!val) { #if defined(RK3188) pio->gpio_swport_dr &= ~offset; #elif defined(AM3352) pio->gpio_cleardataout = offset; #endif } else { #if defined(RK3188) pio->gpio_swport_dr |= offset; #elif defined(AM3352) pio->gpio_setdataout = offset; #endif debug("GPIO_SWPORT_DR: 0x%08lx\n", pio->gpio_dataout); } return 0; }
{ .modalias = "ak4182", .bus_num = 1, .chip_select = 0, .max_speed_hz = 2500000, .irq = gpio_to_irq(MAGUS_GPIO_AK4182), .platform_data = &ak4182, }, }; #include <linux/i2c.h> #include <linux/rtc/s35390a.h> static const struct s35390a_platform_data s35390a = { .irq1 = gpio_to_irq(GPIO_NUM(3, 8)), .irq2 = gpio_to_irq(GPIO_NUM(3, 9)), }; static struct i2c_board_info __initdata _i2c[] = { { I2C_BOARD_INFO("rtc-s35390a", 0x30), .platform_data = &s35390a, }, }; #include <linux/input.h> #include "gpio_vol.h" static gpio_vol_data vol_data =