void init_bp070wx1_lcd(void)
{
printf("bp070wx1 lcd\n");
Delay_ms(20);
GP_COMMAD_PA(3);SPI_WriteData(0xF0);SPI_WriteData(0x5A);SPI_WriteData(0x5A);
GP_COMMAD_PA(3);SPI_WriteData(0xF1);SPI_WriteData(0x5A);SPI_WriteData(0x5A);
GP_COMMAD_PA(3);SPI_WriteData(0xFC);SPI_WriteData(0xA5);SPI_WriteData(0xA5);
GP_COMMAD_PA(2);SPI_WriteData(0xB1);SPI_WriteData(0x10);
GP_COMMAD_PA(5);SPI_WriteData(0xB2);SPI_WriteData(0x14);SPI_WriteData(0x22);SPI_WriteData(0x2F);SPI_WriteData(0x04);
GP_COMMAD_PA(3);SPI_WriteData(0xD0);SPI_WriteData(0x00);SPI_WriteData(0x10);
GP_COMMAD_PA(6);SPI_WriteData(0xF2);SPI_WriteData(0x02);SPI_WriteData(0x08);SPI_WriteData(0x08);SPI_WriteData(0x40);SPI_WriteData(0x10);
GP_COMMAD_PA(2);SPI_WriteData(0xB0);SPI_WriteData(0x03);
GP_COMMAD_PA(3);SPI_WriteData(0xFD);SPI_WriteData(0x23);SPI_WriteData(0x09);
GP_COMMAD_PA(11);SPI_WriteData(0xF3);SPI_WriteData(0x01);SPI_WriteData(0xD7);SPI_WriteData(0xE2);SPI_WriteData(0x62);SPI_WriteData(0xF4);SPI_WriteData(0xF7);SPI_WriteData(0x77);SPI_WriteData(0x3C);SPI_WriteData(0x26);SPI_WriteData(0x00);
GP_COMMAD_PA(46);SPI_WriteData(0xF4);SPI_WriteData(0x00);SPI_WriteData(0x02);SPI_WriteData(0x03);SPI_WriteData(0x26);SPI_WriteData(0x03);SPI_WriteData(0x02);SPI_WriteData(0x09);SPI_WriteData(0x00);SPI_WriteData(0x07);SPI_WriteData(0x16);SPI_WriteData(0x16);SPI_WriteData(0x03);SPI_WriteData(0x00);SPI_WriteData(0x08);SPI_WriteData(0x08);SPI_WriteData(0x03);SPI_WriteData(0x0E);SPI_WriteData(0x0F);SPI_WriteData(0x12);SPI_WriteData(0x1C);SPI_WriteData(0x1D);SPI_WriteData(0x1E);SPI_WriteData(0x0C);SPI_WriteData(0x09);SPI_WriteData(0x01);SPI_WriteData(0x04);SPI_WriteData(0x02);SPI_WriteData(0x61);SPI_WriteData(0x74);SPI_WriteData(0x75);SPI_WriteData(0x72);SPI_WriteData(0x83);SPI_WriteData(0x80);SPI_WriteData(0x80);SPI_WriteData(0xB0);SPI_WriteData(0x00);SPI_WriteData(0x01);SPI_WriteData(0x01);SPI_WriteData(0x28);SPI_WriteData(0x04);SPI_WriteData(0x03);SPI_WriteData(0x28);SPI_WriteData(0x01);SPI_WriteData(0xD1);SPI_WriteData(0x32);
GP_COMMAD_PA(27);SPI_WriteData(0xF5);SPI_WriteData(0x8C);SPI_WriteData(0x2F);SPI_WriteData(0x2F);SPI_WriteData(0x3A);SPI_WriteData(0xAB);SPI_WriteData(0x98);SPI_WriteData(0x52);SPI_WriteData(0x0F);SPI_WriteData(0x33);SPI_WriteData(0x43);SPI_WriteData(0x04);SPI_WriteData(0x59);SPI_WriteData(0x54);SPI_WriteData(0x52);SPI_WriteData(0x05);SPI_WriteData(0x40);SPI_WriteData(0x60);SPI_WriteData(0x4E);SPI_WriteData(0x60);SPI_WriteData(0x40);SPI_WriteData(0x27);SPI_WriteData(0x26);SPI_WriteData(0x52);SPI_WriteData(0x25);SPI_WriteData(0x6D);SPI_WriteData(0x18);
GP_COMMAD_PA(9);SPI_WriteData(0xEE);SPI_WriteData(0x22);SPI_WriteData(0x00);SPI_WriteData(0x22);SPI_WriteData(0x00);SPI_WriteData(0x22);SPI_WriteData(0x00);SPI_WriteData(0x22);SPI_WriteData(0x00);
GP_COMMAD_PA(9);SPI_WriteData(0xEF);SPI_WriteData(0x12);SPI_WriteData(0x12);SPI_WriteData(0x43);SPI_WriteData(0x43);SPI_WriteData(0xA0);SPI_WriteData(0x04);SPI_WriteData(0x24);SPI_WriteData(0x81);
GP_COMMAD_PA(33);SPI_WriteData(0xF7);SPI_WriteData(0x0A);SPI_WriteData(0x0A);SPI_WriteData(0x08);SPI_WriteData(0x08);SPI_WriteData(0x0B);SPI_WriteData(0x0B);SPI_WriteData(0x09);SPI_WriteData(0x09);SPI_WriteData(0x04);SPI_WriteData(0x05);SPI_WriteData(0x01);SPI_WriteData(0x01);SPI_WriteData(0x01);SPI_WriteData(0x01);SPI_WriteData(0x01);SPI_WriteData(0x01);SPI_WriteData(0x0A);SPI_WriteData(0x0A);SPI_WriteData(0x08);SPI_WriteData(0x08);SPI_WriteData(0x0B);SPI_WriteData(0x0B);SPI_WriteData(0x09);SPI_WriteData(0x09);SPI_WriteData(0x04);SPI_WriteData(0x05);SPI_WriteData(0x01);SPI_WriteData(0x01);SPI_WriteData(0x01);SPI_WriteData(0x01);SPI_WriteData(0x01);SPI_WriteData(0x01);
GP_COMMAD_PA(4);SPI_WriteData(0xBC);SPI_WriteData(0x01);SPI_WriteData(0x4E);SPI_WriteData(0x0A);
GP_COMMAD_PA(6);SPI_WriteData(0xE1);SPI_WriteData(0x03);SPI_WriteData(0x10);SPI_WriteData(0x1C);SPI_WriteData(0xA0);SPI_WriteData(0x10);
GP_COMMAD_PA(7);SPI_WriteData(0xF6);SPI_WriteData(0x60);SPI_WriteData(0x25);SPI_WriteData(0xA6);SPI_WriteData(0x00);SPI_WriteData(0x00);SPI_WriteData(0x00);
GP_COMMAD_PA(7);SPI_WriteData(0xFE);SPI_WriteData(0x00);SPI_WriteData(0x0D);SPI_WriteData(0x03);SPI_WriteData(0x21);SPI_WriteData(0x00);SPI_WriteData(0x78);
GP_COMMAD_PA(18);SPI_WriteData(0xFA);SPI_WriteData(0x00);SPI_WriteData(0x35);SPI_WriteData(0x0A);SPI_WriteData(0x12);SPI_WriteData(0x0B);SPI_WriteData(0x11);SPI_WriteData(0x17);SPI_WriteData(0x16);SPI_WriteData(0x19);SPI_WriteData(0x21);SPI_WriteData(0x24);SPI_WriteData(0x24);SPI_WriteData(0x25);SPI_WriteData(0x25);SPI_WriteData(0x24);SPI_WriteData(0x23);SPI_WriteData(0x2B);
GP_COMMAD_PA(18);SPI_WriteData(0xFB);SPI_WriteData(0x00);SPI_WriteData(0x35);SPI_WriteData(0x0A);SPI_WriteData(0x12);SPI_WriteData(0x0A);SPI_WriteData(0x11);SPI_WriteData(0x16);SPI_WriteData(0x16);SPI_WriteData(0x19);SPI_WriteData(0x21);SPI_WriteData(0x24);SPI_WriteData(0x24);SPI_WriteData(0x25);SPI_WriteData(0x25);SPI_WriteData(0x24);SPI_WriteData(0x23);SPI_WriteData(0x2B);
Delay_ms(10);
GP_COMMAD_PA(4);SPI_WriteData(0xC3);SPI_WriteData(0x40);SPI_WriteData(0x00);SPI_WriteData(0x28);
Delay_ms(120);
GP_COMMAD_PA(2);SPI_WriteData(0x35);SPI_WriteData(0x00);
GP_COMMAD_PA(1);SPI_WriteData(0x11);
Delay_ms(200);
GP_COMMAD_PA(1);SPI_WriteData(0x29);
}
void Init_SSD2805_SPI(void)
{
SPI_Init();
Delay_ms(10);
Set_RST(0);// ( rGPFDAT &= (~(1<<3))) ;
Delay_ms(50);
Set_RST(1);// ( rGPFDAT |= (1<<3) ) ;
Delay_ms(10);
//void SPI_2825_WrCmd(U8)
//void SPI_2825_WrReg(U8 c,U16 value)
//Initial code 1: SSD2825 initialization
//RGB interface configuration
SPI_2825_WrReg(0xb1,(LCD_HSPW<<8)|LCD_VSPW); //Vertical sync and horizontal sync active period
SPI_2825_WrReg(0xb2,(LCD_HBPD<<8)|LCD_VBPD); //Vertical and horizontal back porch period
SPI_2825_WrReg(0xb3,(LCD_HFPD<<8)|LCD_VFPD); //Vertical and horizontal front porch period
SPI_2825_WrReg(0xb4, LCD_XSIZE_TFT); //Horizontal active period
SPI_2825_WrReg(0xb5, LCD_YSIZE_TFT); //Vertical active period
//SPI_2825_WrReg(0xb6, 0x2007); //Video mode and video pixel format 888
SPI_2825_WrReg(0xb6, 0x2004); //Video mode and video pixel format 565
//MIPI lane configuration
//00 - 1 lane mode
//01 - 2 lane mode
//10 - 3 lane mode
//11 - 4 lane mode
SPI_2825_WrReg(0xde, 0x0001); //MIPI lane select
//SPI_2825_WrReg(0xDD, (LCD_HFPD<<8)|LCD_VFPD);
//SPI_2825_WrReg(0xd6, 0x0004); //Color order and endianess BGR
SPI_2825_WrReg(0xd6, 0x0005); //Color order and endianess RGB
SPI_2825_WrReg(0xb9, 0x0000); //Disable PLL
SPI_2825_WrReg(0xc4, 0x0001); //BTA setting
//CABC brightness setting
SPI_2825_WrReg(0xe9, 0xff2f); //CABC control
SPI_2825_WrReg(0xeb, 0x0100); //CABC control
//Communicate with LCD driver through MIPI
SPI_2825_WrReg(0xb7, 0x0342); //DCS mode 0342
SPI_2825_WrReg(0xb8, 0x0000); //VC registe
SPI_2825_WrReg(0xbc, 0x0000); //Packet size
SPI_2825_WrCmd(0x11); //LCD driver exit sleep mode
Delay_ms(100);
SPI_2825_WrCmd(0x29); //Set LCD driver display on
// PLL configuration
//SPI_2825_WrReg(0xba, 0x8334); //PLL setting,8028 0x34--52*24/3=416M
SPI_2825_WrReg(0xba, 0x8322); //PLL setting,8028 0x27--39*24/3=312M
SPI_2825_WrReg(0xbb, 0x0006); //LP clock divider
SPI_2825_WrReg(0xb9, 0x0001); //PLL enable
SPI_2825_WrReg(0xb8, 0x0000); //VC register
// SPI_2825_WrReg(0xb7, 0x030B); //Generic mode, HS video mode
Delay_ms(55);
//Initial code 2: LCD driver initialization
//MIPI lane and PLL configuration
SPI_2825_WrReg(0xb9, 0x0001); //PLL enable
SPI_2825_WrReg(0xb7, 0x0150); //Generic mode, LP mode
SPI_2825_WrReg(0xb8, 0x0000); //VC register
//Send command and data through MIPI
//------------------------------------------------------------------------------------------
//----------communicate with lcd driver through mipi----------------------------------------
GP_COMMAD_PA(4);
SPI_WriteData(0xBF);
SPI_WriteData(0x91);
SPI_WriteData(0x61);
SPI_WriteData(0xF2);
GP_COMMAD_PA(3);
SPI_WriteData(0xB3);
SPI_WriteData(0x00);
SPI_WriteData(0x77);
GP_COMMAD_PA(3);
SPI_WriteData(0xB4);
SPI_WriteData(0x00);
SPI_WriteData(0x77);
GP_COMMAD_PA(7);
SPI_WriteData(0xB8);
SPI_WriteData(0x00);
SPI_WriteData(0xA0);
SPI_WriteData(0x01);
SPI_WriteData(0x00);
SPI_WriteData(0xA0);
SPI_WriteData(0x01);
GP_COMMAD_PA(4);
SPI_WriteData(0xBA);
SPI_WriteData(0x3E);
SPI_WriteData(0x23);
SPI_WriteData(0x00);
GP_COMMAD_PA(2);
SPI_WriteData(0xC3);
SPI_WriteData(0x04);
GP_COMMAD_PA(3);
SPI_WriteData(0xC4);
SPI_WriteData(0x30);
SPI_WriteData(0x6A);
GP_COMMAD_PA(39);
SPI_WriteData(0xC8);
SPI_WriteData(0x7E);
SPI_WriteData(0x68);
SPI_WriteData(0x57);
SPI_WriteData(0x49);
SPI_WriteData(0x43);
SPI_WriteData(0x33);
SPI_WriteData(0x35);
SPI_WriteData(0x1C);
SPI_WriteData(0x33);
SPI_WriteData(0x2F);
SPI_WriteData(0x2B);
SPI_WriteData(0x43);
SPI_WriteData(0x2C);
SPI_WriteData(0x31);
SPI_WriteData(0x20);
SPI_WriteData(0x22);
SPI_WriteData(0x1E);
SPI_WriteData(0x1D);
SPI_WriteData(0x03);
SPI_WriteData(0x7E);
SPI_WriteData(0x68);
SPI_WriteData(0x57);
SPI_WriteData(0x49);
SPI_WriteData(0x43);
SPI_WriteData(0x33);
SPI_WriteData(0x35);
SPI_WriteData(0x1C);
SPI_WriteData(0x33);
SPI_WriteData(0x2F);
SPI_WriteData(0x2B);
SPI_WriteData(0x43);
SPI_WriteData(0x2C);
SPI_WriteData(0x31);
SPI_WriteData(0x20);
SPI_WriteData(0x22);
SPI_WriteData(0x1E);
SPI_WriteData(0x1D);
SPI_WriteData(0x03);
GP_COMMAD_PA(10);
SPI_WriteData(0xC7);
SPI_WriteData(0x00);
SPI_WriteData(0x01);
SPI_WriteData(0x31);
SPI_WriteData(0x05);
SPI_WriteData(0x65);
SPI_WriteData(0x2B);
SPI_WriteData(0x12);
SPI_WriteData(0xA5);
SPI_WriteData(0xA5);
GP_COMMAD_PA(17);
SPI_WriteData(0xD4);
SPI_WriteData(0x1E);
SPI_WriteData(0x1F);
SPI_WriteData(0x17);
SPI_WriteData(0x37);
SPI_WriteData(0x06);
SPI_WriteData(0x04);
SPI_WriteData(0x0A);
SPI_WriteData(0x08);
SPI_WriteData(0x00);
SPI_WriteData(0x02);
SPI_WriteData(0x1F);
SPI_WriteData(0x1F);
SPI_WriteData(0x1F);
SPI_WriteData(0x1F);
SPI_WriteData(0x1F);
SPI_WriteData(0x1F);
GP_COMMAD_PA(17);
SPI_WriteData(0xD5);
SPI_WriteData(0x1E);
SPI_WriteData(0x1F);
SPI_WriteData(0x17);
SPI_WriteData(0x37);
SPI_WriteData(0x07);
SPI_WriteData(0x05);
SPI_WriteData(0x0B);
SPI_WriteData(0x09);
SPI_WriteData(0x01);
SPI_WriteData(0x03);
SPI_WriteData(0x1F);
SPI_WriteData(0x1F);
SPI_WriteData(0x1F);
SPI_WriteData(0x1F);
SPI_WriteData(0x1F);
SPI_WriteData(0x1F);
GP_COMMAD_PA(17);
SPI_WriteData(0xD6);
SPI_WriteData(0x1F);
SPI_WriteData(0x13);
SPI_WriteData(0x17);
SPI_WriteData(0x17);
SPI_WriteData(0x07);
SPI_WriteData(0x09);
SPI_WriteData(0x0B);
SPI_WriteData(0x05);
SPI_WriteData(0x03);
SPI_WriteData(0x01);
SPI_WriteData(0x1F);
SPI_WriteData(0x1F);
SPI_WriteData(0x1F);
SPI_WriteData(0x1F);
SPI_WriteData(0x1F);
SPI_WriteData(0x1F);
GP_COMMAD_PA(17);
SPI_WriteData(0xD7);
SPI_WriteData(0x1F);
SPI_WriteData(0x1E);
SPI_WriteData(0x17);
SPI_WriteData(0x17);
SPI_WriteData(0x06);
SPI_WriteData(0x08);
SPI_WriteData(0x0A);
SPI_WriteData(0x04);
SPI_WriteData(0x02);
SPI_WriteData(0x00);
SPI_WriteData(0x1F);
SPI_WriteData(0x1F);
SPI_WriteData(0x1F);
SPI_WriteData(0x1F);
SPI_WriteData(0x1F);
SPI_WriteData(0x1F);
GP_COMMAD_PA(21);
SPI_WriteData(0xD8);
SPI_WriteData(0x20);
SPI_WriteData(0x00);
SPI_WriteData(0x00);
SPI_WriteData(0x30);
SPI_WriteData(0x03);
SPI_WriteData(0x30);
SPI_WriteData(0x01);
SPI_WriteData(0x02);
SPI_WriteData(0x00);
SPI_WriteData(0x01);
SPI_WriteData(0x02);
SPI_WriteData(0x06);
SPI_WriteData(0x70);
SPI_WriteData(0x00);
SPI_WriteData(0x00);
SPI_WriteData(0x73);
SPI_WriteData(0x07);
SPI_WriteData(0x06);
SPI_WriteData(0x70);
SPI_WriteData(0x08);
GP_COMMAD_PA(21);
SPI_WriteData(0xD9);
SPI_WriteData(0x00);
SPI_WriteData(0x0A);
SPI_WriteData(0x0A);
SPI_WriteData(0x80);
SPI_WriteData(0x00);
SPI_WriteData(0x00);
SPI_WriteData(0x06);
SPI_WriteData(0x7B);
SPI_WriteData(0x00);
SPI_WriteData(0x80);
SPI_WriteData(0x00);
SPI_WriteData(0x33);
SPI_WriteData(0x6A);
SPI_WriteData(0x1F);
SPI_WriteData(0x00);
SPI_WriteData(0x00);
SPI_WriteData(0x00);
SPI_WriteData(0x03);
SPI_WriteData(0x7B);
GP_COMMAD_PA(2);
SPI_WriteData(0x35);
SPI_WriteData(0x00);
GP_COMMAD_PA(2);
SPI_WriteData(0x11);
SPI_WriteData(0x00);
Delay_us(5);
GP_COMMAD_PA(2);
SPI_WriteData(0x29);
SPI_WriteData(0x00);
Delay_us(1);
//------------------------------------------------------------------------------------------
//Cmd code 3: Access video mode
//RGB interface configuration
SPI_2825_WrReg(0xb1,(LCD_HSPW<<8)|LCD_VSPW); //Vertical sync and horizontal sync active period
SPI_2825_WrReg(0xb2,(LCD_HBPD<<8)|LCD_VBPD); //Vertical and horizontal back porch period
SPI_2825_WrReg(0xb3,(LCD_HFPD<<8)|LCD_VFPD); //Vertical and horizontal front porch period
SPI_2825_WrReg(0xb4, LCD_XSIZE_TFT); //Horizontal active period
SPI_2825_WrReg(0xb5, LCD_YSIZE_TFT); //Vertical active period
//SPI_2825_WrReg(0xb6, 0x0007); //2007 //Video mode and video pixel format 888
SPI_2825_WrReg(0xb6, 0x2004); //2007 //Video mode and video pixel format 565
//MIPI lane configuration
//00 - 1 lane mode
//01 - 2 lane mode
//10 - 3 lane mode
//11 - 4 lane mode
SPI_2825_WrReg(0xde, 0x0001); //MIPI lane select, 2chl
SPI_2825_WrReg(0xd6, 0x0005); //Color order and endianess
SPI_2825_WrReg(0xb9, 0x0000); //Disable PLL
SPI_2825_WrReg(0xc4, 0x0001); //BTA setting
//CABC brightness setting
SPI_2825_WrReg(0xe9, 0xff2f); //CABC control
SPI_2825_WrReg(0xeb, 0x0100); //CABC control
Delay_ms(22);
//PLL configuration
//FR: bit15~14
//00 每 62.5 < OUT f < 125
//01 每 126 < OUT f < 250
//10 每 251 < OUT f < 500
//11 每 501 < OUT f < 1000
//MS: bit12~8
//Fpre = fin/MS
//NS: bit7~0
//Fout = Fpre*NS
SPI_2825_WrReg(0xba, 0x8324); //PLL setting,8028
SPI_2825_WrReg(0xbb, 0x0006); //LP clock divider,煦けf/ㄗ1+1ㄘ,750MHZ/2 =
SPI_2825_WrReg(0xb9, 0x0001); //PLL enable
SPI_2825_WrReg(0xb8, 0x0000); //VC register
SPI_2825_WrReg(0xb7, 0x030B | 0x0020 ); //Generic mode, HS video mode
}
