void gsc_hw_set_sysreg_writeback(struct gsc_dev *dev) { u32 cfg = readl(SYSREG_GSCBLK_CFG1); cfg |= GSC_BLK_DISP1WB_DEST(dev->id); cfg |= GSC_BLK_GSCL_WB_IN_SRC_SEL(dev->id); cfg |= GSC_BLK_SW_RESET_WB_DEST(dev->id); writel(cfg, SYSREG_GSCBLK_CFG1); }
static void gsc_set_gscblk_fimd_wb(struct gsc_context *ctx, bool enable) { u32 gscblk_cfg; gscblk_cfg = readl(SYSREG_GSCBLK_CFG1); if (enable) gscblk_cfg |= GSC_BLK_DISP1WB_DEST(ctx->id) | GSC_BLK_GSCL_WB_IN_SRC_SEL(ctx->id) | GSC_BLK_SW_RESET_WB_DEST(ctx->id); else gscblk_cfg |= GSC_BLK_PXLASYNC_LO_MASK_WB(ctx->id); writel(gscblk_cfg, SYSREG_GSCBLK_CFG1); }
void gsc_hw_set_pixelasync_reset_wb(struct gsc_dev *dev) { u32 cfg = readl(SYSREG_GSCBLK_CFG1); cfg |= GSC_PXLASYNC_MASK_ALL_WB; cfg &= ~GSC_PXLASYNC_MASK_WB(dev->id); writel(cfg, SYSREG_GSCBLK_CFG1); cfg &= ~GSC_BLK_SW_RESET_WB_DEST(dev->id); writel(cfg, SYSREG_GSCBLK_CFG1); cfg |= GSC_BLK_SW_RESET_WB_DEST(dev->id); writel(cfg, SYSREG_GSCBLK_CFG1); /* * This bit should be masked if DISP0 is off */ cfg |= GSC_PXLASYNC_MASK_ALL_WB; writel(cfg, SYSREG_GSCBLK_CFG1); }