/**
* FchInitEnvUsbXhci - Config XHCI controller before PCI
* emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvUsbXhci (
IN VOID *FchDataPtr
)
{
UINT8 XhciEfuse;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *)FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
if ( LocalCfgPtr->Usb.Xhci1Enable == TRUE ) {
if ( LocalCfgPtr->Misc.S3Resume == 0 ) {
XhciInitBeforePciInit (LocalCfgPtr);
} else {
XhciInitIndirectReg (StdHeader);
}
} else {
//
// for power saving.
//
// add Efuse checking for Xhci enable/disable
XhciEfuse = XHCI_EFUSE_LOCATION;
GetEfuseStatus (&XhciEfuse, StdHeader);
if ((XhciEfuse & (BIT0 + BIT1)) != (BIT0 + BIT1)) {
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, 0xF0FFFBFF, 0x0);
}
}
}
/**
* FchSetUsbEnableReg
* emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchSetUsbEnableReg (
IN FCH_DATA_BLOCK *FchDataPtr
)
{
UINT8 UsbModeReg;
UINT8 XhciEfuse;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *)FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
UsbModeReg = 0;
XhciEfuse = XHCI_EFUSE_LOCATION;
GetEfuseStatus (&XhciEfuse, StdHeader);
if ((XhciEfuse & BIT0 ) == 0) {
if (( FchDataPtr->Usb.Xhci0Enable ) || ( FchDataPtr->Usb.Xhci1Enable )) {
FchDataPtr->Usb.Ohci3Enable = FALSE;
FchDataPtr->Usb.Ehci3Enable = FALSE;
UsbModeReg |= 0x80;
} else {
UsbModeReg &= 0x7F;
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, 0xF0FFFBFF, 0x0);
}
} else {
FchDataPtr->Usb.Xhci0Enable = FALSE;
}
if ((XhciEfuse & BIT1) == BIT1) {
FchDataPtr->Usb.Xhci1Enable = FALSE;
}
if ( FchDataPtr->Usb.Ohci1Enable ) {
UsbModeReg |= 0x01;
}
if ( FchDataPtr->Usb.Ehci1Enable ) {
UsbModeReg |= 0x02;
}
if ( FchDataPtr->Usb.Ohci2Enable ) {
UsbModeReg |= 0x04;
}
if ( FchDataPtr->Usb.Ehci2Enable ) {
UsbModeReg |= 0x08;
}
if ( FchDataPtr->Usb.Ohci3Enable ) {
UsbModeReg |= 0x10;
}
if ( FchDataPtr->Usb.Ehci3Enable ) {
UsbModeReg |= 0x20;
}
if ( FchDataPtr->Usb.Ohci4Enable ) {
UsbModeReg |= 0x40;
}
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF, AccessWidth8, 0, UsbModeReg);
}
/**
* FchXhciPowerSavingProgram - Config XHCI for Power Saving mode
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchXhciPowerSavingProgram (
IN FCH_DATA_BLOCK *FchDataPtr
)
{
UINT8 XhciEfuse;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *)FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
// add Efuse checking for Xhci enable/disable
XhciEfuse = XHCI_EFUSE_LOCATION;
GetEfuseStatus (&XhciEfuse, StdHeader);
if ((XhciEfuse & (BIT0 + BIT1)) != (BIT0 + BIT1)) {
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, 0xF0FFFBFF, 0x0);
}
}
/**
* FchInitResetSataProgram - Config Sata controller during
* Power-On
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitResetSataProgram (
IN VOID *FchDataPtr
)
{
UINT8 SataPortNum;
UINT8 PortStatusByte;
UINT8 EfuseByte;
UINT8 FchSataMode;
UINT8 FchSataInternal100Spread;
FCH_RESET_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
//FchSataMode = LocalCfgPtr->Sata.SATA_MODE.SataMode.SataModeReg;
//New structure need calculate Sata Register value
//
FchSataMode = 0;
if ( LocalCfgPtr->FchReset.SataEnable ) {
FchSataMode |= 0x01;
}
if ( LocalCfgPtr->Sata6AhciCap ) {
FchSataMode |= 0x02;
}
if ( LocalCfgPtr->SataSetMaxGen2 ) {
FchSataMode |= 0x04;
}
if ( LocalCfgPtr->FchReset.IdeEnable ) {
FchSataMode |= 0x08;
}
FchSataMode |= (( LocalCfgPtr->SataClkMode ) << 4 ) ;
LocalCfgPtr->SataModeReg = FchSataMode; ///Save Back to Structure
FchSataInternal100Spread = ( UINT8 ) LocalCfgPtr->SataInternal100Spread;
SataPortNum = 0;
if ( ReadFchChipsetRevision ( StdHeader ) >= FCH_BOLTON ) {
// ECO host link domain may not be reset correctly by device's OOB issue.
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG48 + 3), AccessWidth8, ~(UINT32) BIT6, BIT6, StdHeader);
}
//
// Sata Workaround
//
for ( SataPortNum = 0; SataPortNum < 0x08; SataPortNum++ ) {
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG40 + 2), AccessWidth8, 0xFF, 1 << SataPortNum, StdHeader);
FchStall (2, StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG40 + 2), AccessWidth8, (0xFF ^ (1 << SataPortNum)) , 0x00, StdHeader);
FchStall (2, StdHeader);
}
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG84 + 3), AccessWidth8, ~(UINT32) BIT2, 0, StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REGA0), AccessWidth8, ~(UINT32) (BIT2 + BIT3 + BIT4 + BIT5 + BIT6), BIT2 + BIT3 + BIT4 + BIT5, StdHeader);
//
// Sata Setting for clock mode only
//
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGDA, AccessWidth8, 0, FchSataMode);
if ( FchSataInternal100Spread ) {
RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x1E, AccessWidth8, 0xFF, BIT4);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG84), AccessWidth32, 0xFFFFFFFB, 0x00, StdHeader);
} else {
RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x1E, AccessWidth8, ~(UINT32) BIT4, 0x00);
}
EfuseByte = SATA_FIS_BASE_EFUSE_LOC;
GetEfuseStatus (&EfuseByte, StdHeader);
if (EfuseByte & BIT0) {
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGDA, AccessWidth8, 0xFB, 0x04);
}
ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGDA, AccessWidth8, &PortStatusByte);
if ( ((PortStatusByte & 0xF0) == 0x10) ) {
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_PMIOA_REG08, AccessWidth8, 0, BIT5);
}
if ( FchSataInternal100Spread ) {
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG84), AccessWidth32, 0xFFFFFFFF, 0x04, StdHeader);
}
}
