void setup_timer (void) { if ( IS_865XB() ) REG32(CDBR)=(DIVISOR) << DIVF_OFFSET; // 50B else REG32(CDBR)=(DIVISOR-1) << DIVF_OFFSET; // 51 //REG32(TC0DATA) = (((CPU_CLOCK_RATE/DIVISOR)/HZ)+1) << TCD_OFFSET; REG32(TC0DATA) = (((GetSysClockRate()/DIVISOR)/HZ)+1) << TCD_OFFSET; REG32(TCCNR) = TC0EN | TC0MODE_TIMER; REG32(TCIR)=TCIR_TC0IE; lbc_irq.handler = do_LBC; setup_irq(ICU_LBCT, &lbc_irq); enable_lx4180_irq(ICU_LBCT); timer_irq.handler = timer_interrupt; setup_irq(ICU_TMR, &timer_irq); enable_lx4180_irq(ICU_TMR); }
static __init void nino_timer_setup(struct irqaction *irq) { int c; unsigned int cpu_clock_rate; cpu_clock_rate = GetSysClockRate(); //printk("irqaction %x %s %d\n",irq,__FILE__,__LINE__); irq->dev_id = (void *) irq; #ifdef CONFIG_RTL865XC #if 1 /*NEW_SPEC*/ setup_irq(9, irq); REG32(TCCNR) = 0; /* disable timer before setting CDBR */ REG32(CDBR)=(DIVISOR) << DIVF_OFFSET; REG32(TC0DATA) = (((cpu_clock_rate/DIVISOR)/HZ)) << TCD_OFFSET; #else setup_irq(2, irq); REG32(TCCNR) = 0; /* disable timer before setting CDBR */ REG32(CDBR)=(DIVISOR) << DIVF_OFFSET; REG32(TC0DATA) = (((cpu_clock_rate/DIVISOR)/HZ)) << TCD_OFFSET; #endif #else setup_irq(0, irq); REG32(TCCNR) = 0; /* disable timer before setting CDBR */ REG32(CDBR)=(DIVISOR) << DIVF_OFFSET; REG32(TC0DATA) = (((cpu_clock_rate/DIVISOR)/HZ)) << TCD_OFFSET; #endif /* We must wait n cycles for timer to re-latch the new value of TC1DATA. */ for( c = 0; c < DIVISOR; c++ ); REG32(TCCNR) = TC0EN | TC0MODE_TIMER; REG32(TCIR)=TC0IE; }