UINT8 GfxLibCalculateDidTN ( IN UINT32 Vco, IN AMD_CONFIG_PARAMS *StdHeader ) { UINT32 Divider; UINT32 SystemPllCof; UINT8 Did; ASSERT (Vco != 0); SystemPllCof = GfxLibGetSytemPllCofTN (StdHeader) * 100; Divider = ((SystemPllCof * 100) + (Vco - 1)) / Vco; Did = 0; if (Divider < 200) { } else if (Divider <= 1575) { Did = (UINT8) (Divider / 25); } else if (Divider <= 3150) { Did = (UINT8) ((Divider - 1600) / 50) + 64; } else if (Divider <= 6200) { Did = (UINT8) ((Divider - 3200) / 100) + 96; } else { Did = 0x7f; } return Did; }
UINT32 GfxFmCalculateClock ( IN UINT8 Did, IN AMD_CONFIG_PARAMS *StdHeader ) { UINT32 Divider; UINT32 SystemPllCof; SystemPllCof = GfxLibGetSytemPllCofTN (StdHeader) * 100; if (Did >= 8 && Did <= 0x3F) { Divider = Did * 25; } else if (Did > 0x3F && Did <= 0x5F) { Divider = (Did - 64) * 50 + 1600; } else if (Did > 0x5F && Did <= 0x7E) { Divider = (Did - 96) * 100 + 3200; } else if (Did == 0x7f) { Divider = 128 * 100; } else { ASSERT (FALSE); return 200 * 100; } ASSERT (Divider != 0); return (((SystemPllCof * 100) + (Divider - 1)) / Divider); }
/** * Build integrated info table * * * * @param[in] Gfx Gfx configuration info * @retval AGESA_STATUS */ AGESA_STATUS STATIC GfxIntInfoTableInitTN ( IN GFX_PLATFORM_CONFIG *Gfx ) { AGESA_STATUS Status; AGESA_STATUS AgesaStatus; ATOM_FUSION_SYSTEM_INFO_V2 SystemInfoTableV2; PP_FUSE_ARRAY *PpFuseArray; PCIe_PLATFORM_CONFIG *Pcie; ATOM_PPLIB_POWERPLAYTABLE3 *PpTable; UINT8 Channel; AgesaStatus = AGESA_SUCCESS; IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInitTN Enter\n"); LibAmdMemFill (&SystemInfoTableV2, 0x00, sizeof (ATOM_FUSION_SYSTEM_INFO_V2), GnbLibGetHeader (Gfx)); SystemInfoTableV2.sIntegratedSysInfo.sHeader.usStructureSize = sizeof (ATOM_INTEGRATED_SYSTEM_INFO_V1_7); ASSERT (SystemInfoTableV2.sIntegratedSysInfo.sHeader.usStructureSize == 512); SystemInfoTableV2.sIntegratedSysInfo.sHeader.ucTableFormatRevision = 1; SystemInfoTableV2.sIntegratedSysInfo.sHeader.ucTableContentRevision = 7; SystemInfoTableV2.sIntegratedSysInfo.ulDentistVCOFreq = GfxLibGetSytemPllCofTN (GnbLibGetHeader (Gfx)) * 100; SystemInfoTableV2.sIntegratedSysInfo.ulBootUpUMAClock = Gfx->UmaInfo.MemClock * 100; SystemInfoTableV2.sIntegratedSysInfo.usRequestedPWMFreqInHz = Gfx->LcdBackLightControl; SystemInfoTableV2.sIntegratedSysInfo.ucUMAChannelNumber = ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_INTERLEAVE) == 0) ? 1 : 2; SystemInfoTableV2.sIntegratedSysInfo.ucMemoryType = 3; //DDR3 SystemInfoTableV2.sIntegratedSysInfo.ulBootUpEngineClock = 200 * 100; //Set default engine clock to 200MhZ SystemInfoTableV2.sIntegratedSysInfo.usBootUpNBVoltage = GnbLocateHighestVidIndex (GnbLibGetHeader (Gfx)); SystemInfoTableV2.sIntegratedSysInfo.ulMinEngineClock = 200 * 100; SystemInfoTableV2.sIntegratedSysInfo.usPanelRefreshRateRange = Gfx->DynamicRefreshRate; SystemInfoTableV2.sIntegratedSysInfo.usLvdsSSPercentage = Gfx->LvdsSpreadSpectrum; //Locate PCIe configuration data to get definitions of display connectors SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.sHeader.usStructureSize = sizeof (ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO); SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.sHeader.ucTableFormatRevision = 1; SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.sHeader.ucTableContentRevision = 1; SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.uc3DStereoPinId = Gfx->Gnb3dStereoPinIndex; SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.ucRemoteDisplayConfig = Gfx->GnbRemoteDisplaySupport; SystemInfoTableV2.sIntegratedSysInfo.usExtDispConnInfoOffset = offsetof (ATOM_INTEGRATED_SYSTEM_INFO_V1_7, sExtDispConnInfo); SystemInfoTableV2.sIntegratedSysInfo.ulSB_MMIO_Base_Addr = SbGetSbMmioBaseAddress (GnbLibGetHeader (Gfx)); SystemInfoTableV2.sIntegratedSysInfo.usPCIEClkSSPercentage = Gfx->PcieRefClkSpreadSpectrum; SystemInfoTableV2.sIntegratedSysInfo.ucLvdsMisc = Gfx->LvdsMiscControl.Value; IDS_HDT_CONSOLE (GNB_TRACE, "Lvds Misc control : %x\n", Gfx->LvdsMiscControl.Value); if (Gfx->LvdsMiscControl.Field.TravisLvdsVoltOverwriteEn) { SystemInfoTableV2.sIntegratedSysInfo.gnbgfxline429 = Gfx->gfxplmcfg0 ; IDS_HDT_CONSOLE (GNB_TRACE, "TravisLVDSVoltAdjust : %x\n", Gfx->gfxplmcfg0 ); } SystemInfoTableV2.sIntegratedSysInfo.ulOtherDisplayMisc = Gfx->DisplayMiscControl.Value; IDS_HDT_CONSOLE (GNB_TRACE, "Display Misc control : %x\n", Gfx->DisplayMiscControl.Value); // LVDS SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOnSeqDIGONtoDE_in4Ms = Gfx->LvdsPowerOnSeqDigonToDe; SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms = Gfx->LvdsPowerOnSeqDeToVaryBl; SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms = Gfx->LvdsPowerOnSeqVaryBlToDe; SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOffSeqDEtoDIGON_in4Ms = Gfx->LvdsPowerOnSeqDeToDigon; SystemInfoTableV2.sIntegratedSysInfo.ucLVDSOffToOnDelay_in4Ms = Gfx->LvdsPowerOnSeqOnToOffDelay; SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms = Gfx->LvdsPowerOnSeqVaryBlToBlon; SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms = Gfx->LvdsPowerOnSeqBlonToVaryBl; SystemInfoTableV2.sIntegratedSysInfo.ulLCDBitDepthControlVal = Gfx->LcdBitDepthControlValue; SystemInfoTableV2.sIntegratedSysInfo.usMaxLVDSPclkFreqInSingleLink = Gfx->LvdsMaxPixelClockFreq; Status = PcieLocateConfigurationData (GnbLibGetHeader (Gfx), &Pcie); ASSERT (Status == AGESA_SUCCESS); AGESA_STATUS_UPDATE (Status, AgesaStatus); if (Status == AGESA_SUCCESS) { Status = GfxIntegratedEnumerateAllConnectors ( &SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.sPath[0], Pcie, Gfx ); AGESA_STATUS_UPDATE (Status, AgesaStatus); } SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.uceDPToLVDSRxId = eDP_TO_LVDS_RX_DISABLE; PcieConfigRunProcForAllEngines ( DESCRIPTOR_ALLOCATED | DESCRIPTOR_VIRTUAL | DESCRIPTOR_DDI_ENGINE, GfxIntegrateducEDPToLVDSRxIdCallback, &SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.uceDPToLVDSRxId, Pcie ); // Build PP table PpTable = (ATOM_PPLIB_POWERPLAYTABLE3*) &SystemInfoTableV2.ulPowerplayTable; // Build PP table Status = GfxPowerPlayBuildTable (PpTable, Gfx); AGESA_STATUS_UPDATE (Status, AgesaStatus); // Assign usFormatID to 0x000B to represent Trinity PpTable->usFormatID = 0xB; // Build info from fuses PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Gfx)); ASSERT (PpFuseArray != NULL); if (PpFuseArray != NULL) { // Build Display clock info GfxIntInfoTableInitDispclkTable (PpFuseArray, &SystemInfoTableV2.sIntegratedSysInfo, Gfx); // Build Sclk info table GfxIntInfoTableInitSclkTable (PpFuseArray, &SystemInfoTableV2.sIntegratedSysInfo, Gfx); } else { Status = AGESA_ERROR; AGESA_STATUS_UPDATE (Status, AgesaStatus); } //@todo review if thouse parameters needed // Fill in Nb P-state MemclkFreq Data GfxFillNbPstateMemclkFreqTN (&SystemInfoTableV2.sIntegratedSysInfo, Gfx); // Fill in HTC Data GfxFillHtcDataTN (&SystemInfoTableV2.sIntegratedSysInfo, Gfx); // Fill in NB P states VID GfxFillNbPStateVidTN (&SystemInfoTableV2.sIntegratedSysInfo, Gfx); // Fill in NCLK info //GfxFillNclkInfo (&SystemInfoV1Table.sIntegratedSysInfo, Gfx); // Fill in the M3 arbitration control tables //GfxFillM3ArbritrationControl (&SystemInfoV1Table.sIntegratedSysInfo, Gfx); // Family specific data update // Determine ulGMCRestoreResetTime Status = GfxCalculateRestoreResetTimeTN (&SystemInfoTableV2.sIntegratedSysInfo, Gfx, PpFuseArray); AGESA_STATUS_UPDATE (Status, AgesaStatus); //GfxFmIntegratedInfoTableInit (&SystemInfoV1Table.sIntegratedSysInfo, Gfx); SystemInfoTableV2.sIntegratedSysInfo.ulDDR_DLL_PowerUpTime = 4940; SystemInfoTableV2.sIntegratedSysInfo.ulDDR_PLL_PowerUpTime = 2000; if ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_ON_DCT0) != 0) { Channel = 0; } else { Channel = 1; } if (GfxLibGetMemPhyPllPdModeTN (Channel, GnbLibGetHeader (Gfx)) != 0) { SystemInfoTableV2.sIntegratedSysInfo.ulSystemConfig |= BIT2; } if (GfxLibGetDisDllShutdownSRTN (Channel, GnbLibGetHeader (Gfx)) == 0) { SystemInfoTableV2.sIntegratedSysInfo.ulSystemConfig |= BIT1; } if (GnbBuildOptions.CfgPciePowerGatingFlags != (PCIE_POWERGATING_SKIP_CORE | PCIE_POWERGATING_SKIP_PHY)) { SystemInfoTableV2.sIntegratedSysInfo.ulSystemConfig |= BIT0; } SystemInfoTableV2.sIntegratedSysInfo.ulGPUCapInfo = GPUCAPINFO_TMDS_HDMI_USE_CASCADE_PLL_MODE | GPUCAPINFO_DP_USE_SINGLE_PLL_MODE; IDS_HDT_CONSOLE (GNB_TRACE, "ulSystemConfig : %x\n", SystemInfoTableV2.sIntegratedSysInfo.ulSystemConfig); IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_INTEGRATED_TABLE_CONFIG, &SystemInfoTableV2.sIntegratedSysInfo, GnbLibGetHeader (Gfx)); //Copy integrated info table to Frame Buffer. (Do not use LibAmdMemCopy, routine not guaranteed access to above 4G memory in 32 bit mode.) GfxIntInfoTabablePostToFb (&SystemInfoTableV2, Gfx); IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInit Exit [0x%x]\n", Status); return Status; }