//----------------------------------------------------------------------------- static void uart_init(uint32_t baud) { HAL_GPIO_UART_TX_out(); HAL_GPIO_UART_TX_pmuxen(HAL_GPIO_PMUX_D); HAL_GPIO_UART_RX_in(); HAL_GPIO_UART_RX_pmuxen(HAL_GPIO_PMUX_D); MCLK->APBBMASK.reg |= MCLK_APBBMASK_SERCOM2; GCLK->PCHCTRL[SERCOM2_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN(0) | GCLK_PCHCTRL_CHEN; while (0 == (GCLK->PCHCTRL[SERCOM2_GCLK_ID_CORE].reg & GCLK_PCHCTRL_CHEN)); SERCOM2->USART.CTRLA.reg = SERCOM_USART_CTRLA_DORD | SERCOM_USART_CTRLA_MODE(1/*INT_CLK*/) | SERCOM_USART_CTRLA_RXPO(1/*PAD1*/) | SERCOM_USART_CTRLA_TXPO(0/*PAD0*/) | SERCOM_USART_CTRLA_SAMPR(1); SERCOM2->USART.CTRLB.reg = SERCOM_USART_CTRLB_RXEN | SERCOM_USART_CTRLB_TXEN | SERCOM_USART_CTRLB_CHSIZE(0/*8 bits*/); #define BAUD_VAL (F_CPU / (16 * baud)) #define FP_VAL ((F_CPU / baud - 16 * BAUD_VAL) / 2) SERCOM2->USART.BAUD.reg = SERCOM_USART_BAUD_FRACFP_BAUD(BAUD_VAL) | SERCOM_USART_BAUD_FRACFP_FP(FP_VAL); SERCOM2->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE; }
//----------------------------------------------------------------------------- static void uart_init(uint32_t baud) { uint64_t br = (uint64_t)65536 * (F_CPU - 16 * baud) / F_CPU; HAL_GPIO_UART_TX_out(); HAL_GPIO_UART_TX_pmuxen(PORT_PMUX_PMUXE_C_Val); HAL_GPIO_UART_RX_in(); HAL_GPIO_UART_RX_pmuxen(PORT_PMUX_PMUXE_C_Val); PM->APBCMASK.reg |= PM_APBCMASK_SERCOM0; GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(SERCOM0_GCLK_ID_CORE) | GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN(0); SERCOM0->USART.CTRLA.reg = SERCOM_USART_CTRLA_DORD | SERCOM_USART_CTRLA_MODE_USART_INT_CLK | SERCOM_USART_CTRLA_RXPO(3/*PAD3*/) | SERCOM_USART_CTRLA_TXPO(1/*PAD2*/); SERCOM0->USART.CTRLB.reg = SERCOM_USART_CTRLB_RXEN | SERCOM_USART_CTRLB_TXEN | SERCOM_USART_CTRLB_CHSIZE(0/*8 bits*/); SERCOM0->USART.BAUD.reg = (uint16_t)br+1; SERCOM0->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE; }
//----------------------------------------------------------------------------- static void uart_init(uint32_t baud) { uint64_t br = (uint64_t)65536 * (F_CPU - 16 * baud) / F_CPU; HAL_GPIO_UART_TX_out(); HAL_GPIO_UART_TX_pmuxen(HAL_GPIO_PMUX_D); HAL_GPIO_UART_RX_in(); HAL_GPIO_UART_RX_pmuxen(HAL_GPIO_PMUX_D); MCLK->APBCMASK.reg |= MCLK_APBCMASK_SERCOM4; GCLK->PCHCTRL[SERCOM4_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN(0) | GCLK_PCHCTRL_CHEN; while (0 == (GCLK->PCHCTRL[SERCOM4_GCLK_ID_CORE].reg & GCLK_PCHCTRL_CHEN)); SERCOM4->USART.CTRLA.reg = SERCOM_USART_CTRLA_DORD | SERCOM_USART_CTRLA_MODE(1/*USART_INT_CLK*/) | SERCOM_USART_CTRLA_RXPO(3/*PAD3*/) | SERCOM_USART_CTRLA_TXPO(1/*PAD2*/); SERCOM4->USART.CTRLB.reg = SERCOM_USART_CTRLB_RXEN | SERCOM_USART_CTRLB_TXEN | SERCOM_USART_CTRLB_CHSIZE(0/*8 bits*/); SERCOM4->USART.BAUD.reg = (uint16_t)br; SERCOM4->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE; }