void cmd_display_banner()
{
tfp_printf("\r\n");
tfp_printf("%s","***************************************\r\n");
tfp_printf("BUILD DATE : %s\r\n",__DATE__);
tfp_printf("BUILD TIME : %s\r\n",__TIME__);
tfp_printf("STM32 HAL version : 0x%08X\r\n",HAL_GetHalVersion());
tfp_printf("STM32 Rev. ID : 0x%08X\r\n",HAL_GetREVID());
tfp_printf("STM32 Dev. ID : 0x%08X\r\n",HAL_GetDEVID());
tfp_printf("%s\r\n",cmd_banner);
}
/**
* @brief System Clock Configuration
* The system Clock is configured as follow :
* System Clock source = PLL (HSE)
* SYSCLK(Hz) = 168000000
* HCLK(Hz) = 168000000
* AHB Prescaler = 1
* APB1 Prescaler = 4
* APB2 Prescaler = 2
* HSE Frequency(Hz) = 8000000
* PLL_M = 8
* PLL_N = 336
* PLL_P = 2
* PLL_Q = 7
* VDD(V) = 3.3
* Main regulator output voltage = Scale1 mode
* Flash Latency(WS) = 5
* @param None
* @retval None
*/
static void SystemClock_Config(void)
{
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
/* Enable Power Control clock */
__HAL_RCC_PWR_CLK_ENABLE();
/* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
/* Enable HSE Oscillator and activate PLL with HSE as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 8;
RCC_OscInitStruct.PLL.PLLN = 336;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = 7;
if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
/* Initialization Error */
Error_Handler();
}
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
clocks dividers */
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
{
/* Initialization Error */
Error_Handler();
}
/* STM32F405x/407x/415x/417x Revision Z devices: prefetch is supported */
if (HAL_GetREVID() == 0x1001)
{
/* Enable the Flash prefetch */
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
}
}
/**
* @brief System Clock Configuration
* The system Clock is configured as follow :
* System Clock source = PLL (HSE)
* SYSCLK(Hz) = 168000000
* HCLK(Hz) = 168000000
* AHB Prescaler = 1
* APB1 Prescaler = 4
* APB2 Prescaler = 2
* HSE Frequency(Hz) = 25000000
* PLL_M = 25
* PLL_N = 336
* PLL_P = 2
* PLL_Q = 7
* VDD(V) = 3.3
* Main regulator output voltage = Scale1 mode
* Flash Latency(WS) = 5
* @param None
* @retval None
*/
static void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_ClkInitTypeDef RCC_ClkInitStruct;
/* Enable Power Control clock */
__HAL_RCC_PWR_CLK_ENABLE();
/* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
/* Configure RCC Oscillators: All parameters can be changed according to user’s needs */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 25;
RCC_OscInitStruct.PLL.PLLN = 336;
RCC_OscInitStruct.PLL.PLLP = 2;
RCC_OscInitStruct.PLL.PLLQ = 7;
HAL_RCC_OscConfig (&RCC_OscInitStruct);
/* RCC Clocks: All parameters can be changed according to user’s needs */
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_HCLK |RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
/* STM32F405x/407x/415x/417x Revision Z devices: prefetch is supported */
if (HAL_GetREVID() == 0x1001)
{
/* Enable the Flash prefetch */
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
}
}
/**
* @brief NOR Demo
* @param None
* @retval None
*/
void NOR_demo(void)
{
/* NOR IDs structure */
static NOR_IDTypeDef pNOR_ID;
NOR_SetHint();
/* STM32F427x/437x/429x/439x "Revision 3" devices: FMC dynamic and static
bank switching is allowed */
if (HAL_GetREVID() >= 0x2000) {}
else
{
/* Disable the LCD to avoid the refrech from the SDRAM */
BSP_LCD_DisplayOff();
}
/*##-1- Configure the NOR device ###########################################*/
/* NOR device configuration */
if(BSP_NOR_Init() != NOR_STATUS_OK)
{
ubInitStatus++;
}
/*##-2- Read & check the NOR device IDs ####################################*/
/* Initialize the ID structure */
pNOR_ID.Manufacturer_Code = (uint16_t)0x00;
pNOR_ID.Device_Code1 = (uint16_t)0x00;
pNOR_ID.Device_Code2 = (uint16_t)0x00;
pNOR_ID.Device_Code3 = (uint16_t)0x00;
/* Read the NOR memory ID */
BSP_NOR_Read_ID(&pNOR_ID);
/* Test the NOR ID correctness */
if(pNOR_ID.Manufacturer_Code != (uint16_t)0x0020)
ubIDStatus++;
else if(pNOR_ID.Device_Code1 != (uint16_t)0x227E)
ubIDStatus++;
else if (pNOR_ID.Device_Code2 != (uint16_t)0x2221)
ubIDStatus++;
else if (pNOR_ID.Device_Code3 != (uint16_t)0x2200)
ubIDStatus++;
/*##-3- Erase NOR memory ###################################################*/
/* Return to read mode */
BSP_NOR_ReturnToReadMode();
if(BSP_NOR_Erase_Block(WRITE_READ_ADDR) != NOR_STATUS_OK)
{
ubEraseStatus++;
}
/*##-4- NOR memory read/write access ######################################*/
/* Fill the buffer to write */
Fill_Buffer(nor_aTxBuffer, BUFFER_SIZE, 0xC20F);
/* Write data to the NOR memory */
if(BSP_NOR_WriteData(WRITE_READ_ADDR, nor_aTxBuffer, BUFFER_SIZE) != NOR_STATUS_OK)
{
ubWriteStatus++;
}
/* Read back data from the NOR memory */
if(BSP_NOR_ReadData(WRITE_READ_ADDR, nor_aRxBuffer, BUFFER_SIZE) != NOR_STATUS_OK)
{
ubReadStatus++;
}
/*##-5- Checking data integrity ############################################*/
/* STM32F427x/437x/429x/439x "Revision 3" devices: FMC dynamic and static
bank switching is allowed */
if (HAL_GetREVID() >= 0x2000) {}
else
{
/* Enable the LCD */
BSP_LCD_DisplayOn();
/* SDRAM initialization */
BSP_SDRAM_Init();
}
if(ubIDStatus != 0)
{
BSP_LCD_DisplayStringAt(20, 100, (uint8_t *)"NOR Read ID : FAILED.", LEFT_MODE);
BSP_LCD_DisplayStringAt(20, 115, (uint8_t *)"NOR Test Aborted.", LEFT_MODE);
}
else
{
if(ubInitStatus != 0)
{
BSP_LCD_DisplayStringAt(20, 100, (uint8_t *)"NOR Initialization : FAILED.", LEFT_MODE);
BSP_LCD_DisplayStringAt(20, 115, (uint8_t *)"NOR Test Aborted.", LEFT_MODE);
}
else
{
BSP_LCD_DisplayStringAt(20, 100, (uint8_t *)"NOR Initialization : OK.", LEFT_MODE);
}
if(ubEraseStatus != 0)
{
BSP_LCD_DisplayStringAt(20, 115, (uint8_t *)"NOR ERASE : FAILED.", LEFT_MODE);
BSP_LCD_DisplayStringAt(20, 130, (uint8_t *)"NOR Test Aborted.", LEFT_MODE);
}
else
{
BSP_LCD_DisplayStringAt(20, 115, (uint8_t *)"NOR ERASE : OK. ", LEFT_MODE);
}
if(ubWriteStatus != 0)
{
BSP_LCD_DisplayStringAt(20, 130, (uint8_t *)"NOR WRITE : FAILED.", LEFT_MODE);
BSP_LCD_DisplayStringAt(20, 145, (uint8_t *)"NOR Test Aborted.", LEFT_MODE);
}
else
{
BSP_LCD_DisplayStringAt(20, 130, (uint8_t *)"NOR WRITE : OK. ", LEFT_MODE);
}
if(ubReadStatus != 0)
{
BSP_LCD_DisplayStringAt(20, 145, (uint8_t *)"NOR READ : FAILED.", LEFT_MODE);
BSP_LCD_DisplayStringAt(20, 160, (uint8_t *)"NOR Test Aborted.", LEFT_MODE);
}
else
{
BSP_LCD_DisplayStringAt(20, 145, (uint8_t *)"NOR READ : OK. ", LEFT_MODE);
}
if(Buffercmp(nor_aRxBuffer, nor_aTxBuffer, BUFFER_SIZE) > 0)
{
BSP_LCD_DisplayStringAt(20, 160, (uint8_t *)"NOR COMPARE : FAILED.", LEFT_MODE);
BSP_LCD_DisplayStringAt(20, 175, (uint8_t *)"NOR Test Aborted.", LEFT_MODE);
}
else
{
BSP_LCD_DisplayStringAt(20, 160, (uint8_t *)"NOR Test : OK. ", LEFT_MODE);
}
}
while (1)
{
if(CheckForUserInput() > 0)
{
return;
}
}
}
/**
* @brief Initialize the COMP according to the specified
* parameters in the COMP_InitTypeDef and initialize the associated handle.
* @note If the selected comparator is locked, initialization can't be performed.
* To unlock the configuration, perform a system reset.
* @note When the LPTIM connection is enabled, the following pins LPTIM_IN1(PB5, PC0)
and LPTIM_IN2(PB7, PC2) should not be configured in alternate function.
* @param hcomp COMP handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
{
uint32_t tmp_csr = 0U;
uint32_t exti_line = 0U;
uint32_t comp_voltage_scaler_not_initialized = 0U;
__IO uint32_t wait_loop_index = 0U;
HAL_StatusTypeDef status = HAL_OK;
/* Check the COMP handle allocation and lock status */
if((hcomp == NULL) || (__HAL_COMP_IS_LOCKED(hcomp)))
{
status = HAL_ERROR;
}
else
{
/* Check the parameters */
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
assert_param(IS_COMP_INPUT_PLUS(hcomp->Instance, hcomp->Init.NonInvertingInput));
assert_param(IS_COMP_INPUT_MINUS(hcomp->Instance, hcomp->Init.InvertingInput));
assert_param(IS_COMP_OUTPUTPOL(hcomp->Init.OutputPol));
assert_param(IS_COMP_POWERMODE(hcomp->Init.Mode));
assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode));
assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode));
if(hcomp->State == HAL_COMP_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hcomp->Lock = HAL_UNLOCKED;
/* Init SYSCFG and the low level hardware to access comparators */
/* Note: HAL_COMP_Init() calls __HAL_RCC_SYSCFG_CLK_ENABLE() */
/* to enable internal control clock of the comparators. */
/* However, this is a legacy strategy. In future STM32 families, */
/* COMP clock enable must be implemented by user */
/* in "HAL_COMP_MspInit()". */
/* Therefore, for compatibility anticipation, it is recommended */
/* to implement __HAL_RCC_SYSCFG_CLK_ENABLE() */
/* in "HAL_COMP_MspInit()". */
__HAL_RCC_SYSCFG_CLK_ENABLE();
/* Init the low level hardware */
HAL_COMP_MspInit(hcomp);
}
/* Set COMP parameters */
tmp_csr = (hcomp->Init.InvertingInput |
hcomp->Init.OutputPol );
/* Configuration specific to comparator instance: COMP2 */
if ((hcomp->Instance) == COMP2)
{
/* Comparator input plus configuration is available on COMP2 only */
/* Comparator power mode configuration is available on COMP2 only */
tmp_csr |= (hcomp->Init.NonInvertingInput |
hcomp->Init.Mode );
/* COMP2 specificity: when using VrefInt or subdivision of VrefInt, */
/* specific path must be enabled. */
if((hcomp->Init.InvertingInput == COMP_INPUT_MINUS_VREFINT) ||
(hcomp->Init.InvertingInput == COMP_INPUT_MINUS_1_4VREFINT) ||
(hcomp->Init.InvertingInput == COMP_INPUT_MINUS_1_2VREFINT) ||
(hcomp->Init.InvertingInput == COMP_INPUT_MINUS_3_4VREFINT) )
{
/* Memorize voltage scaler state before initialization */
comp_voltage_scaler_not_initialized = (READ_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP) == 0U);
SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP );
/* Delay for COMP scaler bridge voltage stabilization */
/* Apply the delay if voltage scaler bridge is enabled for the first time */
if (comp_voltage_scaler_not_initialized != 0U)
{
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles. */
wait_loop_index = (COMP_DELAY_VOLTAGE_SCALER_STAB_US * (SystemCoreClock / (1000000U * 2U)));
while(wait_loop_index != 0U)
{
wait_loop_index--;
}
}
}
}
/* Set comparator output connection to LPTIM */
if (hcomp->Init.LPTIMConnection != COMP_LPTIMCONNECTION_DISABLED)
{
/* LPTIM connexion requested on COMP1 */
if ((hcomp->Instance) == COMP1)
{
/* Note : COMP1 can be connected to the input 1 of LPTIM if requested */
assert_param(IS_COMP1_LPTIMCONNECTION(hcomp->Init.LPTIMConnection));
if (hcomp->Init.LPTIMConnection == COMP_LPTIMCONNECTION_IN1_ENABLED)
{
tmp_csr |= (COMP_CSR_COMP1LPTIM1IN1);
}
}
else
{
/* Check the MCU_ID in order to allow or not the COMP2 connection to LPTIM-input2 */
if (((HAL_GetDEVID() == C_DEV_ID_L073) && (HAL_GetREVID() == C_REV_ID_A))
||
((HAL_GetDEVID() == C_DEV_ID_L053) && (HAL_GetREVID() == C_REV_ID_A))
||
((HAL_GetDEVID() == C_DEV_ID_L053) && (HAL_GetREVID() == C_REV_ID_Z)))
{
/* Note : COMP2 can be connected only to input 1 of LPTIM if requested */
assert_param(IS_COMP2_LPTIMCONNECTION_RESTRICTED(hcomp->Init.LPTIMConnection));
tmp_csr |= (COMP_CSR_COMP2LPTIM1IN1);
}
/* LPTIM connexion requested on COMP2 */
else
{
/* Note : COMP2 can be connected to input 1 or input2 of LPTIM if requested */
assert_param(IS_COMP2_LPTIMCONNECTION(hcomp->Init.LPTIMConnection));
switch (hcomp->Init.LPTIMConnection)
{
case COMP_LPTIMCONNECTION_IN1_ENABLED :
tmp_csr |= (COMP_CSR_COMP2LPTIM1IN1);
break;
case COMP_LPTIMCONNECTION_IN2_ENABLED :
tmp_csr |= (COMP_CSR_COMP2LPTIM1IN2);
break;
default :
break;
}
}
}
}
/* Update comparator register */
if ((hcomp->Instance) == COMP1)
{
MODIFY_REG(hcomp->Instance->CSR,
COMP_CSR_COMP1INNSEL | COMP_CSR_COMP1WM |
COMP_CSR_COMP1LPTIM1IN1 | COMP_CSR_COMP1POLARITY ,
tmp_csr
);
}
else /* Instance == COMP2 */
{
MODIFY_REG(hcomp->Instance->CSR,
COMP_CSR_COMP2SPEED | COMP_CSR_COMP2INNSEL |
COMP_CSR_COMP2INPSEL | COMP_CSR_COMP2POLARITY |
COMP_CSR_COMP2LPTIM1IN2 | COMP_CSR_COMP2LPTIM1IN1 ,
tmp_csr
);
}
/* Set window mode */
/* Note: Window mode bit is located into 1 out of the 2 pairs of COMP */
/* instances. Therefore, this function can update another COMP */
/* instance that the one currently selected. */
if(hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)
{
SET_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE);
}
else
{
CLEAR_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE);
}
/* Get the EXTI line corresponding to the selected COMP instance */
exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
/* Manage EXTI settings */
if((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != RESET)
{
/* Configure EXTI rising edge */
if((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != RESET)
{
SET_BIT(EXTI->RTSR, exti_line);
}
else
{
CLEAR_BIT(EXTI->RTSR, exti_line);
}
/* Configure EXTI falling edge */
if((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != RESET)
{
SET_BIT(EXTI->FTSR, exti_line);
}
else
{
CLEAR_BIT(EXTI->FTSR, exti_line);
}
/* Clear COMP EXTI pending bit (if any) */
WRITE_REG(EXTI->PR, exti_line);
/* Configure EXTI event mode */
if((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != RESET)
{
SET_BIT(EXTI->EMR, exti_line);
}
else
{
CLEAR_BIT(EXTI->EMR, exti_line);
}
/* Configure EXTI interrupt mode */
if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != RESET)
{
SET_BIT(EXTI->IMR, exti_line);
}
else
{
CLEAR_BIT(EXTI->IMR, exti_line);
}
}
else
{
/* Disable EXTI event generation */
CLEAR_BIT(EXTI->EMR, exti_line);
}
/* Set HAL COMP handle state */
/* Note: Transition from state reset to state ready, */
/* otherwise (coming from state ready or busy) no state update. */
if (hcomp->State == HAL_COMP_STATE_RESET)
{
hcomp->State = HAL_COMP_STATE_READY;
}
}
return status;
}
/**
* @brief Initializes the COMP according to the specified
* parameters in the COMP_InitTypeDef and create the associated handle.
* @note If the selected comparator is locked, initialization can't be performed.
* To unlock the configuration, perform a system reset.
* @note When the LPTIM connection is enabled, the following pins LPTIM_IN1(PB5, PC0)
and LPTIM_IN2(PB7, PC2) should not be configured in AF.
* @param hcomp: COMP handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the COMP handle allocation and lock status */
if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != 0x00))
{
status = HAL_ERROR;
}
else
{
/* Check the parameter */
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
assert_param(IS_COMP_INVERTINGINPUT(hcomp->Init.InvertingInput));
assert_param(IS_COMP_NONINVERTINGINPUT(hcomp->Init.NonInvertingInput));
assert_param(IS_COMP_OUTPUTPOL(hcomp->Init.OutputPol));
assert_param(IS_COMP_MODE(hcomp->Init.Mode));
if(hcomp->Init.WindowMode != COMP_WINDOWMODE_DISABLE)
{
assert_param(IS_COMP_WINDOWMODE_INSTANCE(hcomp->Instance));
assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode));
}
if(hcomp->State == HAL_COMP_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hcomp->Lock = HAL_UNLOCKED;
/* Init SYSCFG and the low level hardware to access comparators */
__HAL_RCC_SYSCFG_CLK_ENABLE();
/* Init the low level hardware : SYSCFG to access comparators */
HAL_COMP_MspInit(hcomp);
}
/* Change COMP peripheral state */
hcomp->State = HAL_COMP_STATE_BUSY;
/* Set COMP parameters */
/* Set COMPxINSEL bits according to hcomp->Init.InvertingInput value */
/* Set COMPxNONINSEL bits according to hcomp->Init.NonInvertingInput value */
/* Set COMPxLPTIMCONNECTION bits according to hcomp->Init.LPTIMConnection value */
/* Set COMPxPOL bit according to hcomp->Init.OutputPol value */
/* Set COMPxMODE bits according to hcomp->Init.Mode value */
/* Set COMP1WM bit according to hcomp->Init.WindowMode value */
/* No LPTIM connexion requested */
if (hcomp->Init.LPTIMConnection == COMP_LPTIMCONNECTION_DISABLED)
{
MODIFY_REG(hcomp->Instance->CSR, COMP_CSR_UPDATE_PARAMETERS_MASK, \
hcomp->Init.InvertingInput | \
hcomp->Init.NonInvertingInput | \
hcomp->Init.OutputPol | \
hcomp->Init.Mode | \
hcomp->Init.WindowMode);
}
else
{
/* LPTIM connexion requested on COMP2*/
if ((hcomp->Instance) == COMP2)
{
/* Check the MCU_ID in order to allow or not the COMP2 connection to LPTIM-input2 */
if (((HAL_GetDEVID() == C_DEV_ID_L073) && (HAL_GetREVID() == C_REV_ID_A))
||
((HAL_GetDEVID() == C_DEV_ID_L053) && (HAL_GetREVID() == C_REV_ID_A))
||
((HAL_GetDEVID() == C_DEV_ID_L053) && (HAL_GetREVID() == C_REV_ID_Z)))
{
/* Note : COMP2 can be connected only to input 1 of LPTIM if requested */
assert_param(IS_COMP2_LPTIMCONNECTION_RESTRICTED(hcomp->Init.LPTIMConnection));
MODIFY_REG(hcomp->Instance->CSR, COMP_CSR_UPDATE_PARAMETERS_MASK, \
hcomp->Init.InvertingInput | \
hcomp->Init.NonInvertingInput | \
COMP_CSR_COMP2LPTIM1IN1 | \
hcomp->Init.OutputPol | \
hcomp->Init.Mode | \
hcomp->Init.WindowMode);
}
else
{
/* Note : COMP2 can be connected to input 1 or input2 of LPTIM if requested */
assert_param(IS_COMP2_LPTIMCONNECTION(hcomp->Init.LPTIMConnection));
switch (hcomp->Init.LPTIMConnection)
{
case COMP_LPTIMCONNECTION_IN1_ENABLED :
MODIFY_REG(hcomp->Instance->CSR, COMP_CSR_UPDATE_PARAMETERS_MASK, \
hcomp->Init.InvertingInput | \
hcomp->Init.NonInvertingInput | \
COMP_CSR_COMP2LPTIM1IN1 | \
hcomp->Init.OutputPol | \
hcomp->Init.Mode | \
hcomp->Init.WindowMode);
break;
case COMP_LPTIMCONNECTION_IN2_ENABLED :
MODIFY_REG(hcomp->Instance->CSR, COMP_CSR_UPDATE_PARAMETERS_MASK, \
hcomp->Init.InvertingInput | \
hcomp->Init.NonInvertingInput | \
COMP_CSR_COMP2LPTIM1IN2 | \
hcomp->Init.OutputPol | \
hcomp->Init.Mode | \
hcomp->Init.WindowMode);
break;
default :
MODIFY_REG(hcomp->Instance->CSR, COMP_CSR_UPDATE_PARAMETERS_MASK, \
hcomp->Init.InvertingInput | \
hcomp->Init.NonInvertingInput | \
hcomp->Init.OutputPol | \
hcomp->Init.Mode | \
hcomp->Init.WindowMode);
break;
}
}
}
else
/* LPTIM connexion requested on COMP1 */
{
/* Note : COMP1 can be connected to the input 1 of LPTIM if requested */
assert_param(IS_COMP1_LPTIMCONNECTION(hcomp->Init.LPTIMConnection));
if (hcomp->Init.LPTIMConnection == COMP_LPTIMCONNECTION_IN1_ENABLED)
MODIFY_REG(hcomp->Instance->CSR, COMP_CSR_UPDATE_PARAMETERS_MASK, \
hcomp->Init.InvertingInput | \
hcomp->Init.NonInvertingInput | \
COMP_CSR_COMP1LPTIM1IN1 | \
hcomp->Init.OutputPol | \
hcomp->Init.Mode | \
hcomp->Init.WindowMode);
else
MODIFY_REG(hcomp->Instance->CSR, COMP_CSR_UPDATE_PARAMETERS_MASK, \
hcomp->Init.InvertingInput | \
hcomp->Init.NonInvertingInput | \
hcomp->Init.OutputPol | \
hcomp->Init.Mode | \
hcomp->Init.WindowMode);
}
}
/* Initialize the COMP state*/
hcomp->State = HAL_COMP_STATE_READY;
}
return status;
}
/**
* @brief Main program
* @param None
* @retval None
*/
int main(void)
{
/* STM32F4xx HAL library initialization:
- Configure the Flash prefetch, instruction and Data caches
- Configure the Systick to generate an interrupt each 1 msec
- Set NVIC Group Priority to 4
- Global MSP (MCU Support Package) initialization
*/
HAL_Init();
/* Configure LED1, LED2, LED3 and LED4 */
BSP_LED_Init(LED1);
BSP_LED_Init(LED2);
BSP_LED_Init(LED3);
BSP_LED_Init(LED4);
/* Configure Key Button, will be used to trigger an interrupt each time it's pressed.
In the ISR the PLL source will be changed from HSE to HSI, and vice versa. */
BSP_PB_Init(BUTTON_KEY, BUTTON_MODE_EXTI);
/* Enable Power Control clock */
__HAL_RCC_PWR_CLK_ENABLE();
/* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
/* Enable HSE oscillator and configure the PLL to reach the max system frequency (168MHz)
when using HSE oscillator as PLL clock source. */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 25;
RCC_OscInitStruct.PLL.PLLN = 336;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = 7;
if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
/* Initialization Error */
Error_Handler();
}
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers.
The SysTick 1 msec interrupt is required for the HAL process (Timeout management); by default
the configuration is done using the HAL_Init() API, and when the system clock configuration
is updated the SysTick configuration will be adjusted by the HAL_RCC_ClockConfig() API. */
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
{
/* Initialization Error */
Error_Handler();
}
/* STM32F405x/407x/415x/417x Revision Z devices: prefetch is supported */
if (HAL_GetREVID() == 0x1001)
{
/* Enable the Flash prefetch */
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
}
/* Output SYSCLK divided by 2 on MCO2 pin(PC9) */
HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_2);
/* Toggle some LEDs in an infinite loop */
while (1)
{
/* Toggle LED1 */
BSP_LED_Toggle(LED1);
HAL_Delay(100);
/* Toggle LED2 */
BSP_LED_Toggle(LED2);
HAL_Delay(100);
/* Toggle LED4 */
BSP_LED_Toggle(LED4);
HAL_Delay(100);
}
}
static void initClock(void)
{
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
#if defined STM32F1
__HAL_RCC_PWR_CLK_ENABLE();
uint8_t fLatency;
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
RCC_OscInitStruct.HSICalibrationValue = 0;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
# if (defined STM32F100xB) || (defined STM32F100xE)
// 8 MHz * 3 = 24 MHz SYSCLK
RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL3;
fLatency = FLASH_LATENCY_0;
# elif (defined STM32F101x6) || (defined STM32F101xB) || (defined STM32F101xE) || (defined STM32F101xG)
// 8 MHz / 2 * 9 = 36 MHz SYSCLK
RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV2;
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
fLatency = FLASH_LATENCY_1;
# elif (defined STM32F102x6) || (defined STM32F102xB)
// 8 MHz * 6 = 48 MHz SYSCLK
RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6;
fLatency = FLASH_LATENCY_1;
# elif (defined STM32F103x6) || (defined STM32F103xB) || (defined STM32F103xE) || (defined STM32F103xG)
// 8 MHz * 9 = 72 MHz SYSCLK
RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
fLatency = FLASH_LATENCY_2;
# elif (defined STM32F105xC) || (defined STM32F107xC)
// 8 MHz * 9 = 72 MHz SYSCLK
RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
fLatency = FLASH_LATENCY_2;
# endif
HAL_RCC_OscConfig(&RCC_OscInitStruct);
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, fLatency);
#elif defined STM32F2
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 25;
RCC_OscInitStruct.PLL.PLLN = 240;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = 5;
HAL_RCC_OscConfig(&RCC_OscInitStruct);
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
clocks dividers */
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3);
#elif defined STM32F4
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
// 8 MHz * 336 / 8 / 2 = 168 MHz SYSCLK
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 8;
RCC_OscInitStruct.PLL.PLLN = 336;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = 7;
HAL_RCC_OscConfig(&RCC_OscInitStruct);
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV4;
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
if (HAL_GetREVID() == 0x1001)
{
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
}
#endif
}
