// input is the active phase of the chosen interrupt. It is assumed that
// the source is normally level-sensititve rather than edge-sensitive.
static void interferewith( int which, int input )
{
int level, up, hipri, mask, req;
// Interfere with interrupt 'which'
HAL_INTERRUPT_CONFIGURE( which, 1, input ); // should be no change
checkallbut( 0 ); // so don't exclude any of them
HAL_INTERRUPT_CONFIGURE( which, 1, !input ); // make it other-sensitive
DELAY( DLA );
HAL_INTERRUPT_ACKNOWLEDGE( which );
DELAY( DLA );
HAL_INTERRUPT_QUERY_INFO( which, level, up, hipri, mask, req);
CYG_TEST_CHECK( 0 != level , "Int not level-sensitive (-ve level)" );
if ( input )
CYG_TEST_CHECK( 0 == up, "Int high level (-ve level)" );
else
CYG_TEST_CHECK( 0 != up, "Int low level (-ve level)" );
CYG_TEST_CHECK( 0 != mask , "Int unmasked (-ve level)" );
CYG_TEST_CHECK( 0 != req , "Int not requesting (-ve level)" );
checkallbut( which ); // don't check #which, we're messing with it
HAL_INTERRUPT_CONFIGURE( which, 0, input ); // edge, default sense
DELAY( DLA );
HAL_INTERRUPT_ACKNOWLEDGE( which );
DELAY( DLA );
HAL_INTERRUPT_QUERY_INFO( which, level, up, hipri, mask, req);
CYG_TEST_CHECK( 0 == level , "Int not edge-sensitive (+ve edge)" );
if ( input )
CYG_TEST_CHECK( 0 != up, "Int low edge (+ve edge)" );
else
CYG_TEST_CHECK( 0 == up, "Int high edge (+ve edge)" );
CYG_TEST_CHECK( 0 != mask , "Int unmasked (+ve edge)" );
CYG_TEST_CHECK( 0 == req , "Int requesting (+ve edge)" );
checkallbut( which ); // don't check #which, we're messing with it
HAL_INTERRUPT_CONFIGURE( which, 0, !input ); // edge, opposite sense
DELAY( DLA );
HAL_INTERRUPT_ACKNOWLEDGE( which );
DELAY( DLA );
HAL_INTERRUPT_QUERY_INFO( which, level, up, hipri, mask, req);
CYG_TEST_CHECK( 0 == level , "Int not edge-sensitive (-ve edge)" );
if ( input )
CYG_TEST_CHECK( 0 == up, "Int high edge (-ve edge)" );
else
CYG_TEST_CHECK( 0 != up, "Int low edge (-ve edge)" );
CYG_TEST_CHECK( 0 != mask , "Int unmasked (-ve edge)" );
CYG_TEST_CHECK( 0 == req , "Int requesting (-ve edge)" );
checkallbut( which ); // don't check #which, we're messing with it
HAL_INTERRUPT_CONFIGURE( which, 1, input ); // back to original value
DELAY( DLA );
HAL_INTERRUPT_ACKNOWLEDGE( which );
DELAY( DLA );
checkallbut( 0 ); // so don't exclude any of them
}
static int cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, CYG_ADDRWORD vector, CYG_ADDRWORD __data)
{
int res = 0;
cyg_uint32 iir;
cyg_uint8 c;
channel_data_t* chan;
CYGARC_HAL_SAVE_GP();
// Some of the diagnostic print code calls through here with no idea what the ch_data is.
// Go ahead and assume it is channels[0].
if (__ch_data == 0)
__ch_data = (void*)&channels[0];
chan = (channel_data_t*)__ch_data;
HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
iir = RA_UART_REG(chan->base, UART_IIR) & UART_IIR_ID_MASK;
*__ctrlc = 0;
if ((iir == UART_IIR_RX_AVIL) || (iir == UART_IIR_RX_TIMEOUT)) {
c = RA_UART_REG(chan->base, UART_IIR) & 0xFF;
if( cyg_hal_is_break( &c , 1 ) )
*__ctrlc = 1;
res = CYG_ISR_HANDLED;
}
CYGARC_HAL_RESTORE_GP();
return res;
}
static int
cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
int res = 0;
cyg_uint8 eir, c;
channel_data_t* chan = (channel_data_t*)__ch_data;
CYGARC_HAL_SAVE_GP();
HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
HAL_READ_UINT8(chan->base+CYG_DEVICE_BK0_EIR, eir);
*__ctrlc = 0;
if( (eir & CYG_DEVICE_BK0_EIR_mask) == CYG_DEVICE_BK0_EIR_IRQ_RX ) {
HAL_READ_UINT8(chan->base+CYG_DEVICE_BK0_RXD, c);
if( cyg_hal_is_break( &c , 1 ) )
*__ctrlc = 1;
res = CYG_ISR_HANDLED;
}
CYGARC_HAL_RESTORE_GP();
return res;
}
static cyg_bool
cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
{
cyg_uint8* port;
cyg_uint8 _status;
// Some of the diagnostic print code calls through here with no idea what the ch_data is.
// Go ahead and assume it is channels[0].
if (__ch_data == 0)
__ch_data = (void*)&channels[0];
port = ((channel_data_t*)__ch_data)->base;
HAL_READ_UINT8(port + _SERIAL_SR, _status);
if ((_status & SIO_LSTAT_RRDY) == 0)
return false;
HAL_READ_UINT8(port + _SERIAL_RXR, *ch);
// We must ack the interrupt caused by that read to avoid
// confusing the GDB stub ROM.
HAL_INTERRUPT_ACKNOWLEDGE( CYGNUM_HAL_INTERRUPT_SERIAL_0_RX );
return true;
}
static int
cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
int res = 0;
cyg_uint16 status;
cyg_uint16 control;
cyg_uint16 * base = ((channel_data_t *)__ch_data)->base;
CYGARC_HAL_SAVE_GP();
*__ctrlc = 0;
HAL_READ_UINT16(base+CYG_DEV_SERIAL_RS232_SCSR, status);
HAL_READ_UINT16(base+CYG_DEV_SERIAL_RS232_SCCR1, control);
if((status & SCSR_RDRF) && (control & SCCR1_RIE))
{ // Only if the interrupt was caused by the channel
cyg_uint8 c;
c = cyg_hal_plf_serial_getc(__ch_data);
if(cyg_hal_is_break(&c, 1))
*__ctrlc = 1;
HAL_INTERRUPT_ACKNOWLEDGE(((channel_data_t *)__ch_data)->imb3_vector);
res = CYG_ISR_HANDLED;
}
CYGARC_HAL_RESTORE_GP();
return res;
}
static int
cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
channel_data_t* chan = (channel_data_t*)__ch_data;
CYG_ADDRESS esci_base = (CYG_ADDRESS) chan->base;
cyg_uint16 esci_sr;
int res = 0;
cyg_uint8 ch_in;
CYGARC_HAL_SAVE_GP();
*__ctrlc = 0;
HAL_READ_UINT16(FREESCALE_ESCI_SR(esci_base), esci_sr);
if (esci_sr & FREESCALE_ESCI_SR_RDRF) {
HAL_READ_UINT8(FREESCALE_ESCI_DRL(esci_base), ch_in);
if( cyg_hal_is_break( (char *) &ch_in , 1 ) )
*__ctrlc = 1;
res = CYG_ISR_HANDLED;
HAL_WRITE_UINT16(FREESCALE_ESCI_SR(esci_base), FREESCALE_ESCI_SR_RDRF);
}
HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
CYGARC_HAL_RESTORE_GP();
return res;
}
static int cyg_hal_plf_duart_isr(void *__ch_data, int* __ctrlc,
CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
channel_data_t* chan = (channel_data_t*)__ch_data;
uart_width _iir;
int res = 0;
CYGARC_HAL_SAVE_GP();
HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IIR, _iir);
_iir &= SIO_IIR_ID_MASK;
*__ctrlc = 0;
if ( ISR_Rx == _iir ) {
uart_width c, lsr;
cyg_uint8 c8;
HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_LSR, lsr);
if (lsr & SIO_LSR_DR) {
HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_RHR, c);
c8 = (cyg_uint8) (c & 0x00FF);
if (cyg_hal_is_break( &c8 , 1 ))
*__ctrlc = 1;
}
// Acknowledge the interrupt
HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
res = CYG_ISR_HANDLED;
}
CYGARC_HAL_RESTORE_GP();
return res;
}
static int CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR
cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
channel_data_t* chan = (channel_data_t*)__ch_data;
CYG_ADDRESS uart_p = (CYG_ADDRESS) chan->base;
cyg_uint8 uart_s1;
int res = 0;
cyg_uint8 ch_in;
CYGARC_HAL_SAVE_GP();
*__ctrlc = 0;
HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_S1, uart_s1);
if (uart_s1 & CYGHWR_DEV_FREESCALE_UART_S1_RDRF) {
HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_D, ch_in);
if( cyg_hal_is_break( (char *) &ch_in , 1 ) )
*__ctrlc = 1;
res = CYG_ISR_HANDLED;
}
HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
CYGARC_HAL_RESTORE_GP();
return res;
}
static int
cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
int res = 0;
cyg_uint8 _iir, c;
channel_data_t* chan;
CYGARC_HAL_SAVE_GP();
// Some of the diagnostic print code calls through here with no idea what the ch_data is.
// Go ahead and assume it is channels[0].
if (__ch_data == 0)
__ch_data = (void*)&channels[0];
chan = (channel_data_t*)__ch_data;
HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
HAL_READ_UINT8(chan->base + SER_16550_IIR, _iir);
_iir &= SIO_IIR_ID_MASK;
*__ctrlc = 0;
if ((_iir == ISR_Rx_Avail) || (_iir == ISR_Rx_Char_Timeout)) {
HAL_READ_UINT8(chan->base + SER_16550_RBR, c);
if( cyg_hal_is_break( &c , 1 ) )
*__ctrlc = 1;
res = CYG_ISR_HANDLED;
}
CYGARC_HAL_RESTORE_GP();
return res;
}
static int
cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_uint8 iir;
int res = 0;
CYGARC_HAL_SAVE_GP();
HAL_READ_UINT8(chan->base+PXA2X0_UART_IIR, iir);
iir &= PXA2X0_UART_IIR_ID_MASK;
*__ctrlc = 0;
if ( iir == 0x04 ) {
cyg_uint8 c, lsr;
HAL_READ_UINT8(chan->base+PXA2X0_UART_LSR, lsr);
if (lsr & PXA2X0_UART_LSR_DR) {
HAL_READ_UINT8(chan->base+PXA2X0_UART_RBR, c);
if( cyg_hal_is_break( &c , 1 ) )
*__ctrlc = 1;
}
// Acknowledge the interrupt
HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
res = CYG_ISR_HANDLED;
}
CYGARC_HAL_RESTORE_GP();
return res;
}
//===========================================================================
// Serial channel ISR
//===========================================================================
static int cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
int res = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_uint8 c;
cyg_uint8 iir;
CYGARC_HAL_SAVE_GP();
*__ctrlc = 0;
HAL_READ_UINT32(chan->base + CYGARC_HAL_LPC24XX_REG_UxIIR, iir);
if((iir & (CYGARC_HAL_LPC24XX_REG_UxIIR_IIR0 |
CYGARC_HAL_LPC24XX_REG_UxIIR_IIR1 |
CYGARC_HAL_LPC24XX_REG_UxIIR_IIR2))
== CYGARC_HAL_LPC24XX_REG_UxIIR_IIR2)
{
// Rx data available or character timeout
// Read data in order to clear interrupt
HAL_READ_UINT32(chan->base + CYGARC_HAL_LPC24XX_REG_UxRBR, c);
if( cyg_hal_is_break( &c , 1 ) ) *__ctrlc = 1;
res = CYG_ISR_HANDLED;
}
HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
CYGARC_HAL_RESTORE_GP();
return res;
}
static int
cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
int res = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_uint8 c;
cyg_uint8 stat;
CYGARC_HAL_SAVE_GP();
*__ctrlc = 0;
HAL_READ_UINT32(chan->base+CYGARC_HAL_LPC2XXX_REG_UxLSR, stat);
if ( (stat & CYGARC_HAL_LPC2XXX_REG_UxLSR_RDR) != 0 ) {
HAL_READ_UINT32(chan->base+CYGARC_HAL_LPC2XXX_REG_UxRBR, c);
if( cyg_hal_is_break( &c , 1 ) )
*__ctrlc = 1;
res = CYG_ISR_HANDLED;
}
HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
CYGARC_HAL_RESTORE_GP();
return res;
}
static int
cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
int res = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_uint32 c;
cyg_uint8 ch;
cyg_uint32 stat;
CYGARC_HAL_SAVE_GP();
*__ctrlc = 0;
HAL_READ_UINT32(chan->base+AT91_US_CSR, stat);
if ( (stat & AT91_US_CSR_RxRDY) != 0 ) {
HAL_READ_UINT32(chan->base+AT91_US_RHR, c);
ch = (cyg_uint8)(c & 0xff);
if( cyg_hal_is_break( &ch , 1 ) )
*__ctrlc = 1;
res = CYG_ISR_HANDLED;
}
HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
CYGARC_HAL_RESTORE_GP();
return res;
}
cyg_uint32 hal_ctrlc_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data)
{
// char c;
HAL_INTERRUPT_ACKNOWLEDGE( CYGHWR_HAL_GDB_PORT_VECTOR );
return 2;
}
// Periodic timer ISR.
static cyg_uint32
isr_pit(CYG_ADDRWORD vector, CYG_ADDRWORD data, HAL_SavedRegisters *regs)
{
HAL_INTERRUPT_ACKNOWLEDGE (CYGNUM_HAL_INTERRUPT_SIU_PIT);
__profile_hit(regs->pc);
return Cyg_InterruptHANDLED;
}
static int
cyg_hal_plf_serial_isr(channel_data_t *chan, int *ctrlc,
CYG_ADDRWORD vector, CYG_ADDRWORD data)
{
chan->ctrlc = ctrlc;
XUartNs550_InterruptHandler(&chan->dev);
HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
return CYG_ISR_HANDLED;
}
// Profiling timer ISR
static cyg_uint32 profile_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data, HAL_SavedRegisters *regs)
{
cyg_uint32 status;
HAL_READ_UINT32(AT91_TC+AT91_TC_PROFILE+AT91_TC_SR, status); // Clear interrupt
HAL_INTERRUPT_ACKNOWLEDGE(HAL_INTERRUPT_PROFILE);
__profile_hit(regs->pc);
return CYG_ISR_HANDLED;
}
static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
cyg_uint16 ser_port_reg;
int ret = 0;
va_list ap;
CYGARC_HAL_SAVE_GP();
va_start(ap, __func);
switch (__func) {
case __COMMCTL_GETBAUD:
ret = chan->baud_rate;
break;
case __COMMCTL_SETBAUD:
chan->baud_rate = va_arg(ap, cyg_int32);
// Should we verify this value here?
cyg_hal_plf_serial_init_channel(chan);
ret = 0;
break;
case __COMMCTL_IRQ_ENABLE:
irq_state = 1;
HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
HAL_INTERRUPT_UNMASK(chan->isr_vector);
HAL_READ_UINT16(FREESCALE_ESCI_CR12(base), ser_port_reg);
ser_port_reg |= FREESCALE_ESCI_CR12_RIE;
HAL_WRITE_UINT16(FREESCALE_ESCI_CR12(base), ser_port_reg);
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
HAL_INTERRUPT_MASK(chan->isr_vector);
HAL_READ_UINT16(FREESCALE_ESCI_CR12(base), ser_port_reg);
ser_port_reg &= ~(cyg_uint16)FREESCALE_ESCI_CR12_RIE;
HAL_WRITE_UINT16(FREESCALE_ESCI_CR12(base), ser_port_reg);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector;
break;
case __COMMCTL_SET_TIMEOUT:
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
default:
break;
}
va_end(ap);
CYGARC_HAL_RESTORE_GP();
return ret;
}
static int CYGOPT_HAL_KINETIS_DIAG_FLASH_SECTION_ATTR
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
channel_data_t* chan = (channel_data_t*)__ch_data;
CYG_ADDRESS uart_p = ((channel_data_t*)__ch_data)->base;
cyg_uint8 ser_port_reg;
int ret = 0;
va_list ap;
CYGARC_HAL_SAVE_GP();
va_start(ap, __func);
switch (__func) {
case __COMMCTL_IRQ_ENABLE:
chan->irq_state = 1;
HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
HAL_INTERRUPT_UNMASK(chan->isr_vector);
HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg);
ser_port_reg |= CYGHWR_DEV_FREESCALE_UART_C2_RIE;
HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg);
break;
case __COMMCTL_IRQ_DISABLE:
ret = chan->irq_state;
chan->irq_state = 0;
HAL_INTERRUPT_MASK(chan->isr_vector);
HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg);
ser_port_reg &= ~(cyg_uint8)CYGHWR_DEV_FREESCALE_UART_C2_RIE;
HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector;
break;
case __COMMCTL_SET_TIMEOUT:
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
case __COMMCTL_GETBAUD:
ret = chan->baud_rate;
break;
case __COMMCTL_SETBAUD:
chan->baud_rate = va_arg(ap, cyg_int32);
// Should we verify this value here?
cyg_hal_plf_serial_init_channel(chan);
ret = 0;
break;
default:
break;
}
va_end(ap);
CYGARC_HAL_RESTORE_GP();
return ret;
}
externC void cyg_drv_interrupt_acknowledge( cyg_vector_t vector )
{
// CYG_REPORT_FUNCTION();
CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");
CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector");
HAL_INTERRUPT_ACKNOWLEDGE( vector );
// CYG_REPORT_RETURN();
}
void hal_diag_read_char_serial1(char *c)
{
register volatile cyg_uint16 *volatile tty_status = SERIAL1_SR;
register volatile cyg_uint8 *volatile tty_rx = SERIAL1_RXR;
while( (*tty_status & SIO1_LSTAT_RRDY) == 0 ) continue;
*c = *tty_rx;
// We must ack the interrupt caused by that read to avoid
// confusing the GDB stub ROM.
HAL_INTERRUPT_ACKNOWLEDGE( CYGNUM_HAL_INTERRUPT_SERIAL_1_RX );
}
cyg_uint32 isr( cyg_uint32 vector, CYG_ADDRWORD data )
{
CYG_TEST_CHECK( ISR_DATA == data , "Bad data passed to ISR");
CYG_TEST_CHECK( CYGNUM_HAL_INTERRUPT_RTC == vector ,
"Bad vector passed to ISR");
HAL_CLOCK_RESET( vector, CYGNUM_HAL_RTC_PERIOD );
HAL_INTERRUPT_ACKNOWLEDGE( vector );
ticks++;
return CYG_ISR_HANDLED;
}
void hal_diag_read_char_serial2(char *c)
{
register volatile cyg_uint8 *volatile tty_status = SERIAL2_SR;
register volatile cyg_uint8 *volatile tty_rx = SERIAL2_RXR;
while( (*tty_status & SIO2_LSTAT_RRDY) == 0 ) continue;
*c = *tty_rx;
#if !defined(CYGSEM_HAL_USE_ROM_MONITOR_CygMon)
// We must ack the interrupt caused by that read to avoid
// confusing the stubs.
HAL_INTERRUPT_ACKNOWLEDGE( CYGNUM_HAL_INTERRUPT_SERIAL_2_RX );
#endif
}
static int
cyg_hal_sccx_isr(void *__ch_data, int* __ctrlc,
CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
EPPC *eppc = eppc_base();
volatile struct cp_bufdesc *bd;
struct port_info *info = (struct port_info *)__ch_data;
volatile struct scc_regs *regs = (volatile struct scc_regs *)((char *)eppc + info->regs);
volatile struct uart_pram *uart_pram = (volatile struct uart_pram *)((char *)eppc + info->pram);
char ch;
int res = 0;
CYGARC_HAL_SAVE_GP();
*__ctrlc = 0;
if (regs->scc_scce & QUICC_SMCE_RX) {
regs->scc_scce = QUICC_SMCE_RX;
/* rx buffer descriptors */
bd = info->next_rxbd;
if ((bd->ctrl & QUICC_BD_CTL_Ready) == 0) {
// then there be a character waiting
ch = bd->buffer[0];
bd->length = 1;
bd->ctrl |= QUICC_BD_CTL_Ready | QUICC_BD_CTL_Int;
if (bd->ctrl & QUICC_BD_CTL_Wrap) {
bd = (struct cp_bufdesc *)((char *)eppc + uart_pram->rbase);
} else {
bd++;
}
info->next_rxbd = bd;
if( cyg_hal_is_break( &ch , 1 ) )
*__ctrlc = 1;
}
// Interrupt handled. Acknowledge it.
HAL_INTERRUPT_ACKNOWLEDGE(info->intnum);
res = CYG_ISR_HANDLED;
}
CYGARC_HAL_RESTORE_GP();
return res;
}
void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
{
cyg_uint32 val;
*((unsigned long*)0xbf000004) = 0x5678; //hack, kick the wd
//clear interrupt if there is any.
HAL_READ_UINT32(TIMER1_INT_STATUS, val);
if(val & 0x1) //if there is an interrupt, clear it
HAL_READ_UINT32(TIMER1_EOI, val);
// HAL_INTERRUPT_ACKNOWLEDGE doesn't do anything, we keep it here
// for code integraty for future porting.
HAL_INTERRUPT_ACKNOWLEDGE(CYGNUM_HAL_INTERRUPT_RTC);
if (period != _period) {
hal_clock_initialize(period);
}
_period = period;
}
static cyg_bool
cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
{
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_uint8* base = chan->base;
cyg_uint32 stat;
cyg_uint32 c;
HAL_READ_UINT32(base+E7T_UART_STAT, stat);
if ((stat & E7T_UART_STAT_RDR) == 0)
return false;
HAL_READ_UINT32(base+E7T_UART_RXBUF, c);
*ch = (cyg_uint8)(c & 0xff);
HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector_rx);
return true;
}
cyg_uint32 hal_ctrlc_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data)
{
char c;
cyg_uint16 sr;
HAL_INTERRUPT_ACKNOWLEDGE( CYGHWR_HAL_GDB_PORT_VECTOR );
HAL_READ_UINT16( SERIAL_SR, sr );
if( sr & SIO_LSTAT_RRDY )
{
HAL_READ_UINT8( SERIAL_RXR, c);
if( cyg_hal_is_break( &c , 1 ) )
cyg_hal_user_break( (CYG_ADDRWORD *)hal_saved_interrupt_state );
}
return 1;
}
static int
cyg_hal_plf_smcx_isr(void *__ch_data, int* __ctrlc,
CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
struct port_info *info = (struct port_info *)__ch_data;
volatile struct smc_regs_8260 *regs = (volatile struct smc_regs_8260*)((char *)IMM + info->regs);
t_Smc_Pram *pram = (t_Smc_Pram *)((char *)IMM + info->pram);
char ch;
int res = 0;
volatile struct cp_bufdesc *bd;
*__ctrlc = 0;
if (regs->smc_smce & SMCE_Rx) {
regs->smc_smce = SMCE_Rx;
/* rx buffer descriptors */
bd = info->next_rxbd;
if ((bd->ctrl & _BD_CTL_Ready) == 0) {
// then there be a character waiting
ch = bd->buffer[0];
bd->length = 1;
bd->ctrl |= _BD_CTL_Ready | _BD_CTL_Int;
if (bd->ctrl & _BD_CTL_Wrap) {
bd = (struct cp_bufdesc *)((char *)IMM + pram->rbase);
} else {
bd++;
}
info->next_rxbd = bd;
if( cyg_hal_is_break( &ch , 1 ) )
*__ctrlc = 1;
}
// Interrupt handled. Acknowledge it.
HAL_INTERRUPT_ACKNOWLEDGE(info->intnum);
res = CYG_ISR_HANDLED;
}
return res;
}
static int
cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
int res = 0;
cyg_uint8 _iir, c;
channel_data_t* chan;
CYGARC_HAL_SAVE_GP();
// Some of the diagnostic print code calls through here with no idea what the ch_data is.
// Go ahead and assume it is channels[0].
if (__ch_data == 0)
__ch_data = (void*)&channels[0];
chan = (channel_data_t*)__ch_data;
HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
HAL_READ_UINT8(chan->base + SER_16550_IIR, _iir);
_iir &= SIO_IIR_ID_MASK;
*__ctrlc = 0;
if ((_iir == ISR_Rx_Avail) || (_iir == ISR_Rx_Char_Timeout)) {
HAL_READ_UINT8(chan->base + SER_16550_RBR, c);
if( cyg_hal_is_break( &c , 1 ) )
*__ctrlc = 1;
res = CYG_ISR_HANDLED;
}
/* sfurman - Hmmm. Under or1ksim, we sometimes receive interrupts
when no characters are in the FIFO. I think this is a SW bug
and not a problem w/ or1ksim, but until the problem is solved,
we always consume the interrupt */
res = CYG_ISR_HANDLED;
CYGARC_HAL_RESTORE_GP();
return res;
}
static int
hal_a2fxxx_serial_isr(void *__ch_data, int* __ctrlc,
CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_uint8 ch;
CYGARC_HAL_SAVE_GP();
*__ctrlc = 0;
if( hal_a2fxxx_serial_getc_nonblock(__ch_data, &ch) )
{
if( cyg_hal_is_break( (char *)&ch , 1 ) )
*__ctrlc = 1;
}
HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
CYGARC_HAL_RESTORE_GP();
return 1;
}
