void hdmi_msm_powerdown_phy(void) { /* Disable PLL */ HDMI_OUTP_ND(0x030C, 0x00); /* Power down PHY */ HDMI_OUTP_ND(0x0308, 0x7F); /*0b01111111*/ }
void hdmi_msm_powerdown_phy(void) { /* Assert RESET PHY from controller */ HDMI_OUTP_ND(0x02D4, 0x4); udelay(10); /* De-assert RESET PHY from controller */ HDMI_OUTP_ND(0x02D4, 0x0); /* Turn off Driver */ HDMI_OUTP_ND(0x0308, 0x1F); udelay(10); /* Disable PLL */ HDMI_OUTP_ND(0x030C, 0x00); /* Power down PHY */ HDMI_OUTP_ND(0x0308, 0x7F); /*0b01111111*/ }
void hdmi_msm_powerdown_phy(void) { HDMI_OUTP_ND(0x02D4, 0x4); udelay(10); HDMI_OUTP_ND(0x02D4, 0x0); HDMI_OUTP_ND(0x0308, 0x1F); udelay(10); HDMI_OUTP_ND(0x030C, 0x00); HDMI_OUTP_ND(0x0308, 0x7F); }
void hdmi_msm_powerdown_phy(void) { /* Disable PLL */ HDMI_OUTP_ND(0x030C, 0x00); #ifdef WORKAROUND_FOR_HDMI_CURRENT_LEAKAGE_FIX HDMI_OUTP_ND(0x02D4, 0x4); //Assert RESET PHY from controller udelay(10); HDMI_OUTP_ND(0x02D4, 0x0); //De-assert RESET PHY from controller HDMI_OUTP_ND(0x0308, 0x1F); //Turn off Driver udelay(10); #endif /* Power down PHY */ //HDMI_OUTP_ND(0x0308, 0x7F); /*0b01111111*/ HDMI_OUTP_ND(0x0308, 0xFF); /*0b11111111*/ }
void hdmi_msm_powerdown_phy(void) { /* Power down PHY */ HDMI_OUTP_ND(HDMI_PHY_REG_2, 0x7F); /*0b01111111*/ }
void hdmi_msm_init_phy(int video_format) { uint32 offset; /* De-serializer delay D/C for non-lbk mode * PHY REG0 = (DESER_SEL(0) | DESER_DEL_CTRL(3) * | AMUX_OUT_SEL(0)) */ HDMI_OUTP_ND(0x0300, 0x0C); /*0b00001100*/ if (video_format == HDMI_VFRMT_720x480p60_16_9) { /* PHY REG1 = DTEST_MUX_SEL(5) | PLL_GAIN_SEL(0) * | OUTVOL_SWING_CTRL(3) */ HDMI_OUTP_ND(0x0304, 0x53); /*0b01010011*/ } else { /* If the freq. is less than 120MHz, use low gain 0 * for board with termination * PHY REG1 = DTEST_MUX_SEL(5) | PLL_GAIN_SEL(0) * | OUTVOL_SWING_CTRL(4) */ HDMI_OUTP_ND(0x0304, 0x54); /*0b01010100*/ } /* No matter what, start from the power down mode * PHY REG2 = PD_PWRGEN | PD_PLL | PD_DRIVE_4 | PD_DRIVE_3 * | PD_DRIVE_2 | PD_DRIVE_1 | PD_DESER */ HDMI_OUTP_ND(0x0308, 0x7F); /*0b01111111*/ /* Turn PowerGen on * PHY REG2 = PD_PLL | PD_DRIVE_4 | PD_DRIVE_3 * | PD_DRIVE_2 | PD_DRIVE_1 | PD_DESER */ HDMI_OUTP_ND(0x0308, 0x3F); /*0b00111111*/ /* Turn PLL power on * PHY REG2 = PD_DRIVE_4 | PD_DRIVE_3 * | PD_DRIVE_2 | PD_DRIVE_1 | PD_DESER */ HDMI_OUTP_ND(0x0308, 0x1F); /*0b00011111*/ /* Write to HIGH after PLL power down de-assert * PHY REG3 = PLL_ENABLE */ HDMI_OUTP_ND(0x030C, 0x01); /* ASIC power on; PHY REG9 = 0 */ HDMI_OUTP_ND(0x0324, 0x00); /* Enable PLL lock detect, PLL lock det will go high after lock * Enable the re-time logic * PHY REG12 = PLL_LOCK_DETECT_EN | RETIMING_ENABLE */ HDMI_OUTP_ND(0x0330, 0x03); /*0b00000011*/ /* Drivers are on * PHY REG2 = PD_DESER */ HDMI_OUTP_ND(0x0308, 0x01); /*0b00000001*/ /* If the RX detector is needed * PHY REG2 = RCV_SENSE_EN | PD_DESER */ HDMI_OUTP_ND(0x0308, 0x81); /*0b10000001*/ offset = 0x0310; while (offset <= 0x032C) { HDMI_OUTP(offset, 0x0); offset += 0x4; } /* If we want to use lock enable based on counting * PHY REG12 = FORCE_LOCK | PLL_LOCK_DETECT_EN | RETIMING_ENABLE */ HDMI_OUTP_ND(0x0330, 0x13); /*0b00010011*/ }
void hdmi_msm_init_phy(int video_format) { uint32 offset; HDMI_OUTP_ND(0x0300, 0x0C); if (video_format == HDMI_VFRMT_720x480p60_16_9) { HDMI_OUTP_ND(0x0304, 0x53); } else { HDMI_OUTP_ND(0x0304, 0x54); } HDMI_OUTP_ND(0x0308, 0x7F); HDMI_OUTP_ND(0x0308, 0x3F); HDMI_OUTP_ND(0x0308, 0x1F); HDMI_OUTP_ND(0x030C, 0x01); HDMI_OUTP_ND(0x0324, 0x00); HDMI_OUTP_ND(0x0330, 0x03); HDMI_OUTP_ND(0x0308, 0x01); HDMI_OUTP_ND(0x0308, 0x81); offset = 0x0310; while (offset <= 0x032C) { HDMI_OUTP(offset, 0x0); offset += 0x4; } HDMI_OUTP_ND(0x0330, 0x13); }
void hdmi_msm_powerdown_phy(void) { HDMI_OUTP_ND(HDMI_PHY_REG_2, 0x7F); }