sw_error_t
garuda_acl_rule_read(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t vlu[8],
a_uint32_t msk[8])
{
sw_error_t rv;
a_uint32_t i, base, addr;
/* get rule value */
base = GARUDA_RULE_VLU_ADDR + (rule_idx << 5);
for (i = 0; i < 5; i++) {
addr = base + (i << 2);
HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
(a_uint8_t *) (&(vlu[i])),
sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
}
/* get rule mask */
base = GARUDA_RULE_MSK_ADDR + (rule_idx << 5);
for (i = 0; i < 5; i++) {
addr = base + (i << 2);
HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
(a_uint8_t *) (&(msk[i])),
sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
}
return SW_OK;
}
static sw_error_t
_isis_filter_up_to_sw(a_uint32_t dev_id, hw_filter_t * filter,
a_uint32_t flt_idx)
{
#ifdef ISIS_SW_ENTRY
a_uint8_t *tbl = sw_filter_mem + sizeof (hw_filter_t) * flt_idx;
aos_mem_copy(filter, tbl, sizeof (hw_filter_t));
#else
#ifdef ISIS_HW_ENTRY
sw_error_t rv;
a_uint32_t i, base, addr;
base = ISIS_FILTER_VLU_ADDR + (flt_idx << 5);
for (i = 0; i < 5; i++) {
addr = base + (i << 2);
HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
(a_uint8_t *) (&(filter->vlu[i])),
sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
}
base = ISIS_FILTER_MSK_ADDR + (flt_idx << 5);
for (i = 0; i < 5; i++) {
addr = base + (i << 2);
HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
(a_uint8_t *) (&(filter->msk[i])),
sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
}
base = ISIS_FILTER_ACT_ADDR + (flt_idx << 4);
for (i = 0; i < 3; i++) {
addr = base + (i << 2);
HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
(a_uint8_t *) (&(filter->act[i])),
sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
}
#else
sw_error_t rv;
rv = _isis_filter_read(dev_id, &(filter->vlu[0]), flt_idx,
ISIS_FILTER_VLU_OP);
SW_RTN_ON_ERROR(rv);
rv = _isis_filter_read(dev_id, &(filter->msk[0]), flt_idx,
ISIS_FILTER_MSK_OP);
SW_RTN_ON_ERROR(rv);
rv = _isis_filter_read(dev_id, &(filter->act[0]), flt_idx,
ISIS_FILTER_ACT_OP);
SW_RTN_ON_ERROR(rv);
#endif
#endif
return SW_OK;
}
static sw_error_t
_shiva_fdb_iterate(a_uint32_t dev_id, a_uint32_t * iterator, fal_fdb_entry_t * entry)
{
a_uint32_t index, addr, data, tbl[3] = { 0 };
sw_error_t rv;
if ((NULL == iterator) || (NULL == entry))
{
return SW_BAD_PTR;
}
if (SHIVA_FDB_ENTRY_NUM == *iterator)
{
return SW_NO_MORE;
}
if (SHIVA_FDB_ENTRY_NUM < *iterator)
{
return SW_BAD_PARAM;
}
for (index = *iterator; index < SHIVA_FDB_ENTRY_NUM; index++)
{
addr = SHIVA_FDB_ENTRY_ADDR2 + (index << 4);
HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
(a_uint8_t *) (&(tbl[2])), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
SW_GET_FIELD_BY_REG(FDB_TABLE_FUNC2, FDB_STATUS, data, tbl[2]);
if (data)
{
addr = SHIVA_FDB_ENTRY_ADDR0 + (index << 4);
HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
(a_uint8_t *) (&(tbl[0])), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
addr = SHIVA_FDB_ENTRY_ADDR1 + (index << 4);
HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
(a_uint8_t *) (&(tbl[1])), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
_shiva_fdb_hw_to_sw(tbl, entry);
break;
}
}
if (SHIVA_FDB_ENTRY_NUM == index)
{
return SW_NO_MORE;
}
*iterator = index + 1;
return SW_OK;
}
static sw_error_t
_isis_filter_read(a_uint32_t dev_id, a_uint32_t reg[], a_uint32_t flt_idx,
a_uint32_t op)
{
a_uint32_t i, addr, data, idx = 6;
sw_error_t rv;
addr = ISIS_RULE_FUNC_ADDR;
data = (flt_idx & 0x7f) | (op << 8) | (0x1 << 10) | (0x1 << 31);
HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
(a_uint8_t *) (&data), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (ISIS_FILTER_ACT_OP == op) {
idx = 4;
}
for (i = 1; i < idx; i++) {
addr = ISIS_RULE_FUNC_ADDR + (i << 2);
HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
(a_uint8_t *) (&(reg[i - 1])),
sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
}
return SW_OK;
}
static sw_error_t
_isis_filter_ports_bind(a_uint32_t dev_id, a_uint32_t flt_idx, a_uint32_t ports)
{
#ifdef ISIS_SW_ENTRY
hw_filter_t filter;
_isis_filter_up_to_sw(dev_id, &filter, flt_idx);
filter.vlu[4] &= 0xffffff80;
filter.vlu[4] |= (ports & 0x7f);
_isis_filter_down_to_hw(dev_id, &filter, flt_idx);
return SW_OK;
#else
#ifdef ISIS_HW_ENTRY
hw_filter_t filter;
filter = sw_rule_ent[dev_id][flt_idx].filter;
filter.vlu[4] &= 0xffffff80;
filter.vlu[4] |= (ports & 0x7f);
_isis_filter_down_to_hw(dev_id, &filter, flt_idx);
return SW_OK;
#else
sw_error_t rv;
a_uint32_t addr, data;
/* read filter value at first */
addr = ISIS_RULE_FUNC_ADDR;
data = (flt_idx & 0x7f) | (0x1 << 10) | (0x1 << 31);
HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
(a_uint8_t *) (&data), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
/* get filter value and modify it */
addr = ISIS_RULE_FUNC_ADDR + 20;
HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
(a_uint8_t *) (&data), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
data &= 0xffffff80;
data |= (ports & 0x7f);
HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
(a_uint8_t *) (&data), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
/* write back filter value */
addr = ISIS_RULE_FUNC_ADDR;
data = (flt_idx & 0x7f) | (0x1 << 31);
HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
(a_uint8_t *) (&data), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
return SW_OK;
#endif
#endif
}
sw_error_t
garuda_acl_action_read(a_uint32_t dev_id, a_uint32_t act_idx,
a_uint32_t * act)
{
sw_error_t rv;
a_uint32_t addr;
/* get rule action */
addr = GARUDA_RULE_ACT_ADDR + (act_idx << 5);
HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
(a_uint8_t *) act, sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
return SW_OK;
}
static sw_error_t
_horus_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
led_pattern_id_t id, led_ctrl_pattern_t * pattern)
{
a_uint32_t data = 0, reg, tmp;
a_uint32_t addr;
sw_error_t rv;
HSL_DEV_ID_CHECK(dev_id);
if (group >= LED_GROUP_BUTT)
{
return SW_BAD_PARAM;
}
if (id > MAX_LED_PATTERN_ID)
{
return SW_BAD_PARAM;
}
if ((LED_MAC_PORT_GROUP == group) && (0 != id))
{
return SW_BAD_PARAM;
}
aos_mem_zero(pattern, sizeof(led_ctrl_pattern_t));
if (LED_MAC_PORT_GROUP == group)
{
addr = LED_PATTERN_ADDR + 8;
}
else
{
addr = LED_PATTERN_ADDR + (id << 2);
}
HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
(a_uint8_t *) (®),
sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (LED_WAN_PORT_GROUP == group)
{
data = (reg >> 16) & 0xffff;
}
sw_error_t
garuda_acl_slct_read(a_uint32_t dev_id, a_uint32_t slct_idx,
a_uint32_t slct[8])
{
sw_error_t rv;
a_uint32_t i, base, addr;
base = GARUDA_RULE_SLCT_ADDR + (slct_idx << 5);
/* get filter address and enable */
for (i = 0; i < 7; i++) {
addr = base + (i << 2);
HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
(a_uint8_t *) (&(slct[i])),
sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
}
return SW_OK;
}
static sw_error_t
_horus_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
led_pattern_id_t id, led_ctrl_pattern_t * pattern)
{
a_uint32_t data = 0, reg, mode;
a_uint32_t addr;
sw_error_t rv;
HSL_DEV_ID_CHECK(dev_id);
if (group >= LED_GROUP_BUTT)
{
return SW_BAD_PARAM;
}
if (id > MAX_LED_PATTERN_ID)
{
return SW_BAD_PARAM;
}
if ((LED_MAC_PORT_GROUP == group) && (0 != id))
{
return SW_BAD_PARAM;
}
if (LED_MAC_PORT_GROUP == group)
{
addr = LED_PATTERN_ADDR + 8;
}
else
{
addr = LED_PATTERN_ADDR + (id << 2);
}
if (LED_ALWAYS_OFF == pattern->mode)
{
mode = 0;
}
else if (LED_ALWAYS_BLINK == pattern->mode)
{
mode = 1;
}
else if (LED_ALWAYS_ON == pattern->mode)
{
mode = 2;
}
else if (LED_PATTERN_MAP_EN == pattern->mode)
{
mode = 3;
}
else
{
return SW_BAD_PARAM;
}
SW_SET_REG_BY_FIELD(LED_CTRL, PATTERN_EN, mode, data);
if (pattern->map & (1 << FULL_DUPLEX_LIGHT_EN))
{
SW_SET_REG_BY_FIELD(LED_CTRL, FULL_LIGHT_EN, 1, data);
}
if (pattern->map & (1 << HALF_DUPLEX_LIGHT_EN))
{
SW_SET_REG_BY_FIELD(LED_CTRL, HALF_LIGHT_EN, 1, data);
}
if (pattern->map & (1 << POWER_ON_LIGHT_EN))
{
SW_SET_REG_BY_FIELD(LED_CTRL, POWERON_LIGHT_EN, 1, data);
}
if (pattern->map & (1 << LINK_1000M_LIGHT_EN))
{
SW_SET_REG_BY_FIELD(LED_CTRL, GE_LIGHT_EN, 1, data);
}
if (pattern->map & (1 << LINK_100M_LIGHT_EN))
{
SW_SET_REG_BY_FIELD(LED_CTRL, FE_LIGHT_EN, 1, data);
}
if (pattern->map & (1 << LINK_10M_LIGHT_EN))
{
SW_SET_REG_BY_FIELD(LED_CTRL, ETH_LIGHT_EN, 1, data);
}
if (pattern->map & (1 << COLLISION_BLINK_EN))
{
SW_SET_REG_BY_FIELD(LED_CTRL, COL_BLINK_EN, 1, data);
}
if (pattern->map & (1 << RX_TRAFFIC_BLINK_EN))
{
SW_SET_REG_BY_FIELD(LED_CTRL, RX_BLINK_EN, 1, data);
}
if (pattern->map & (1 << TX_TRAFFIC_BLINK_EN))
{
SW_SET_REG_BY_FIELD(LED_CTRL, TX_BLINK_EN, 1, data);
}
if (pattern->map & (1 << LINKUP_OVERRIDE_EN))
{
SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 1, data);
}
else
{
SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 0, data);
}
if (LED_BLINK_2HZ == pattern->freq)
{
SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 0, data);
}
else if (LED_BLINK_4HZ == pattern->freq)
{
SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 1, data);
}
else if (LED_BLINK_8HZ == pattern->freq)
{
SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 2, data);
}
else if (LED_BLINK_TXRX == pattern->freq)
{
SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 3, data);
}
else
{
return SW_BAD_PARAM;
}
HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
(a_uint8_t *) (®),
sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (LED_WAN_PORT_GROUP == group)
{
reg &= 0xffff;
reg |= (data << 16);
}
else
{
reg &= 0xffff0000;
reg |= data;
}
HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
(a_uint8_t *) (®),
sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (LED_WAN_PORT_GROUP == group)
{
return SW_OK;
}
HSL_REG_ENTRY_GET(rv, dev_id, LED_PATTERN, 0,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (LED_LAN_PORT_GROUP == group)
{
if (id)
{
SW_SET_REG_BY_FIELD(LED_PATTERN, P3L1_MODE, mode, data);
SW_SET_REG_BY_FIELD(LED_PATTERN, P2L1_MODE, mode, data);
SW_SET_REG_BY_FIELD(LED_PATTERN, P1L1_MODE, mode, data);
}
else
{
SW_SET_REG_BY_FIELD(LED_PATTERN, P3L0_MODE, mode, data);
SW_SET_REG_BY_FIELD(LED_PATTERN, P2L0_MODE, mode, data);
SW_SET_REG_BY_FIELD(LED_PATTERN, P1L0_MODE, mode, data);
}
}
else
{
SW_SET_REG_BY_FIELD(LED_PATTERN, M5_MODE, mode, data);
}
HSL_REG_ENTRY_SET(rv, dev_id, LED_PATTERN, 0,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
return SW_OK;
}
static sw_error_t
_isis_sec_norm_item_get(a_uint32_t dev_id, fal_norm_item_t item, void *value)
{
sw_error_t rv;
a_uint32_t addr, offset, len, reg, val;
a_uint32_t status_chk = 0, val_chk = 0, scmd_chk = 0;
HSL_DEV_ID_CHECK(dev_id);
len = 1;
switch (item)
{
case FAL_NORM_MAC_RESV_VID_CMD:
addr = NORM_CTRL0_ADDR;
offset = 0;
break;
case FAL_NORM_MAC_INVALID_SRC_ADDR_CMD:
addr = NORM_CTRL1_ADDR;
offset = 20;
break;
case FAL_NORM_IP_INVALID_VER_CMD:
addr = NORM_CTRL0_ADDR;
offset = 1;
break;
case FAL_NROM_IP_SAME_ADDR_CMD:
addr = NORM_CTRL0_ADDR;
offset = 2;
break;
case FAL_NROM_IP_TTL_CHANGE_STATUS:
addr = NORM_CTRL3_ADDR;
offset = 11;
status_chk = 1;
break;
case FAL_NROM_IP_TTL_VALUE:
addr = NORM_CTRL3_ADDR;
offset = 12;
len = 8;
val_chk = 1;
break;
case FAL_NROM_IP4_INVALID_HL_CMD:
addr = NORM_CTRL0_ADDR;
offset = 2;
break;
case FAL_NROM_IP4_HDR_OPTIONS_CMD:
addr = NORM_CTRL0_ADDR;
offset = 4;
len = 2;
scmd_chk = 1;
break;
case FAL_NROM_IP4_INVALID_DF_CMD:
addr = NORM_CTRL0_ADDR;
offset = 7;
break;
case FAL_NROM_IP4_FRAG_OFFSET_MIN_LEN_CMD:
addr = NORM_CTRL0_ADDR;
offset = 8;
break;
case FAL_NROM_IP4_FRAG_OFFSET_MIN_SIZE:
addr = NORM_CTRL1_ADDR;
offset = 24;
len = 8;
val_chk = 1;
break;
case FAL_NROM_IP4_FRAG_OFFSET_MAX_LEN_CMD:
addr = NORM_CTRL0_ADDR;
offset = 9;
break;
case FAL_NROM_IP4_INVALID_FRAG_OFFSET_CMD:
addr = NORM_CTRL0_ADDR;
offset = 10;
break;
case FAL_NROM_IP4_INVALID_SIP_CMD:
addr = NORM_CTRL0_ADDR;
offset = 11;
len = 1;
break;
case FAL_NROM_IP4_INVALID_DIP_CMD:
addr = NORM_CTRL0_ADDR;
offset = 12;
break;
case FAL_NROM_IP4_INVALID_CHKSUM_CMD:
addr = NORM_CTRL0_ADDR;
offset = 13;
break;
case FAL_NROM_IP4_INVALID_PL_CMD:
addr = NORM_CTRL1_ADDR;
offset = 19;
break;
case FAL_NROM_IP4_DF_CLEAR_STATUS:
addr = NORM_CTRL3_ADDR;
offset = 9;
status_chk = 1;
break;
case FAL_NROM_IP4_IPID_RANDOM_STATUS:
addr = NORM_CTRL3_ADDR;
offset = 10;
status_chk = 1;
break;
case FAL_NROM_IP6_INVALID_DIP_CMD:
addr = NORM_CTRL1_ADDR;
offset = 16;
break;
case FAL_NROM_IP6_INVALID_SIP_CMD:
addr = NORM_CTRL1_ADDR;
offset = 17;
break;
case FAL_NROM_IP6_INVALID_PL_CMD:
addr = NORM_CTRL1_ADDR;
offset = 18;
break;
case FAL_NROM_TCP_BLAT_CMD:
addr = NORM_CTRL0_ADDR;
offset = 14;
break;
case FAL_NROM_TCP_INVALID_HL_CMD:
addr = NORM_CTRL0_ADDR;
offset = 15;
break;
case FAL_NROM_TCP_MIN_HDR_SIZE:
addr = NORM_CTRL1_ADDR;
offset = 12;
len = 4;
val_chk = 1;
break;
case FAL_NROM_TCP_INVALID_SYN_CMD:
addr = NORM_CTRL0_ADDR;
offset = 16;
break;
case FAL_NROM_TCP_SU_BLOCK_CMD:
addr = NORM_CTRL0_ADDR;
offset = 17;
break;
case FAL_NROM_TCP_SP_BLOCK_CMD:
addr = NORM_CTRL0_ADDR;
offset = 18;
break;
case FAL_NROM_TCP_SAP_BLOCK_CMD:
addr = NORM_CTRL0_ADDR;
offset = 19;
break;
case FAL_NROM_TCP_XMAS_SCAN_CMD:
addr = NORM_CTRL0_ADDR;
offset = 20;
break;
case FAL_NROM_TCP_NULL_SCAN_CMD:
addr = NORM_CTRL0_ADDR;
offset = 21;
break;
case FAL_NROM_TCP_SR_BLOCK_CMD:
addr = NORM_CTRL0_ADDR;
offset = 22;
break;
case FAL_NROM_TCP_SF_BLOCK_CMD:
addr = NORM_CTRL0_ADDR;
offset = 23;
break;
case FAL_NROM_TCP_SAR_BLOCK_CMD:
addr = NORM_CTRL0_ADDR;
offset = 24;
break;
case FAL_NROM_TCP_RST_SCAN_CMD:
addr = NORM_CTRL0_ADDR;
offset = 25;
break;
case FAL_NROM_TCP_SYN_WITH_DATA_CMD:
addr = NORM_CTRL0_ADDR;
offset = 26;
break;
case FAL_NROM_TCP_RST_WITH_DATA_CMD:
addr = NORM_CTRL0_ADDR;
offset = 27;
break;
case FAL_NROM_TCP_FA_BLOCK_CMD:
addr = NORM_CTRL0_ADDR;
offset = 28;
break;
case FAL_NROM_TCP_PA_BLOCK_CMD:
addr = NORM_CTRL0_ADDR;
offset = 29;
break;
case FAL_NROM_TCP_UA_BLOCK_CMD:
addr = NORM_CTRL1_ADDR;
offset = 0;
break;
case FAL_NROM_TCP_INVALID_CHKSUM_CMD:
addr = NORM_CTRL1_ADDR;
offset = 1;
break;
case FAL_NROM_TCP_INVALID_URGPTR_CMD:
addr = NORM_CTRL1_ADDR;
offset = 2;
break;
case FAL_NROM_TCP_INVALID_OPTIONS_CMD:
addr = NORM_CTRL1_ADDR;
offset = 3;
break;
case FAL_NROM_UDP_BLAT_CMD:
addr = NORM_CTRL1_ADDR;
offset = 4;
break;
case FAL_NROM_UDP_INVALID_LEN_CMD:
addr = NORM_CTRL1_ADDR;
offset = 5;
break;
case FAL_NROM_UDP_INVALID_CHKSUM_CMD:
addr = NORM_CTRL1_ADDR;
offset = 6;
break;
case FAL_NROM_ICMP4_PING_PL_EXCEED_CMD:
addr = NORM_CTRL1_ADDR;
offset = 7;
break;
case FAL_NROM_ICMP6_PING_PL_EXCEED_CMD:
addr = NORM_CTRL1_ADDR;
offset = 8;
break;
case FAL_NROM_ICMP4_PING_FRAG_CMD:
addr = NORM_CTRL1_ADDR;
offset = 9;
break;
case FAL_NROM_ICMP6_PING_FRAG_CMD:
addr = NORM_CTRL1_ADDR;
offset = 10;
break;
case FAL_NROM_ICMP4_PING_MAX_PL_VALUE:
addr = NORM_CTRL2_ADDR;
offset = 0;
len = 14;
val_chk = 1;
break;
case FAL_NROM_ICMP6_PING_MAX_PL_VALUE:
addr = NORM_CTRL2_ADDR;
offset = 16;
len = 14;
val_chk = 1;
break;
default:
return SW_BAD_PARAM;
}
HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
(a_uint8_t *) (®), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
SW_FIELD_GET_BY_REG_U32(reg, val, offset, len);
if (val_chk)
{
*((a_uint32_t *) value) = val;
}
else if (status_chk)
{
if (val)
{
*((a_bool_t *) value) = A_TRUE;
}
else
{
*((a_bool_t *) value) = A_FALSE;
}
}
else if (scmd_chk)
{
if (2 == val)
{
*((fal_fwd_cmd_t *) value) = FAL_MAC_RDT_TO_CPU;
}
else if (3 == val)
{
*((fal_fwd_cmd_t *) value) = FAL_MAC_DROP;
}
else
{
*((fal_fwd_cmd_t *) value) = FAL_MAC_FRWRD;
}
}
else
{
if (val)
{
*((fal_fwd_cmd_t *) value) = FAL_MAC_DROP;
}
else
{
*((fal_fwd_cmd_t *) value) = FAL_MAC_FRWRD;
}
}
return SW_OK;
}
static sw_error_t
_isis_sec_norm_item_set(a_uint32_t dev_id, fal_norm_item_t item, void *value)
{
sw_error_t rv;
fal_fwd_cmd_t cmd;
a_bool_t enable;
a_uint32_t addr, offset, len, reg, val;
HSL_DEV_ID_CHECK(dev_id);
cmd = *((fal_fwd_cmd_t *) value);
enable = *((a_bool_t *) value);
val = *((a_uint32_t *) value);
len = 1;
switch (item)
{
case FAL_NORM_MAC_RESV_VID_CMD:
addr = NORM_CTRL0_ADDR;
offset = 0;
goto cmd_chk;
case FAL_NORM_MAC_INVALID_SRC_ADDR_CMD:
addr = NORM_CTRL1_ADDR;
offset = 20;
goto cmd_chk;
case FAL_NORM_IP_INVALID_VER_CMD:
addr = NORM_CTRL0_ADDR;
offset = 1;
goto cmd_chk;
case FAL_NROM_IP_SAME_ADDR_CMD:
addr = NORM_CTRL0_ADDR;
offset = 2;
goto cmd_chk;
break;
case FAL_NROM_IP_TTL_CHANGE_STATUS:
addr = NORM_CTRL3_ADDR;
offset = 11;
goto sts_chk;
case FAL_NROM_IP_TTL_VALUE:
addr = NORM_CTRL3_ADDR;
offset = 12;
len = 8;
goto set_reg;
case FAL_NROM_IP4_INVALID_HL_CMD:
addr = NORM_CTRL0_ADDR;
offset = 3;
goto cmd_chk;
case FAL_NROM_IP4_HDR_OPTIONS_CMD:
addr = NORM_CTRL0_ADDR;
offset = 4;
len = 2;
goto s_cmd_chk;
case FAL_NROM_IP4_INVALID_DF_CMD:
addr = NORM_CTRL0_ADDR;
offset = 7;
goto cmd_chk;
case FAL_NROM_IP4_FRAG_OFFSET_MIN_LEN_CMD:
addr = NORM_CTRL0_ADDR;
offset = 8;
goto cmd_chk;
case FAL_NROM_IP4_FRAG_OFFSET_MIN_SIZE:
addr = NORM_CTRL1_ADDR;
offset = 24;
len = 8;
goto set_reg;
case FAL_NROM_IP4_FRAG_OFFSET_MAX_LEN_CMD:
addr = NORM_CTRL0_ADDR;
offset = 9;
goto cmd_chk;
case FAL_NROM_IP4_INVALID_FRAG_OFFSET_CMD:
addr = NORM_CTRL0_ADDR;
offset = 10;
goto cmd_chk;
case FAL_NROM_IP4_INVALID_SIP_CMD:
addr = NORM_CTRL0_ADDR;
offset = 11;
len = 1;
goto cmd_chk;
case FAL_NROM_IP4_INVALID_DIP_CMD:
addr = NORM_CTRL0_ADDR;
offset = 12;
goto cmd_chk;
case FAL_NROM_IP4_INVALID_CHKSUM_CMD:
addr = NORM_CTRL0_ADDR;
offset = 13;
goto cmd_chk;
case FAL_NROM_IP4_INVALID_PL_CMD:
addr = NORM_CTRL1_ADDR;
offset = 19;
goto cmd_chk;
case FAL_NROM_IP4_DF_CLEAR_STATUS:
addr = NORM_CTRL3_ADDR;
offset = 9;
goto sts_chk;
case FAL_NROM_IP4_IPID_RANDOM_STATUS:
addr = NORM_CTRL3_ADDR;
offset = 10;
goto sts_chk;
case FAL_NROM_IP6_INVALID_DIP_CMD:
addr = NORM_CTRL1_ADDR;
offset = 16;
goto cmd_chk;
case FAL_NROM_IP6_INVALID_SIP_CMD:
addr = NORM_CTRL1_ADDR;
offset = 17;
goto cmd_chk;
case FAL_NROM_IP6_INVALID_PL_CMD:
addr = NORM_CTRL1_ADDR;
offset = 18;
goto cmd_chk;
case FAL_NROM_TCP_BLAT_CMD:
addr = NORM_CTRL0_ADDR;
offset = 14;
goto cmd_chk;
case FAL_NROM_TCP_INVALID_HL_CMD:
addr = NORM_CTRL0_ADDR;
offset = 15;
goto cmd_chk;
case FAL_NROM_TCP_MIN_HDR_SIZE:
addr = NORM_CTRL1_ADDR;
offset = 12;
len = 4;
goto set_reg;
case FAL_NROM_TCP_INVALID_SYN_CMD:
addr = NORM_CTRL0_ADDR;
offset = 16;
goto cmd_chk;
break;
case FAL_NROM_TCP_SU_BLOCK_CMD:
addr = NORM_CTRL0_ADDR;
offset = 17;
goto cmd_chk;
case FAL_NROM_TCP_SP_BLOCK_CMD:
addr = NORM_CTRL0_ADDR;
offset = 18;
goto cmd_chk;
case FAL_NROM_TCP_SAP_BLOCK_CMD:
addr = NORM_CTRL0_ADDR;
offset = 19;
goto cmd_chk;
case FAL_NROM_TCP_XMAS_SCAN_CMD:
addr = NORM_CTRL0_ADDR;
offset = 20;
goto cmd_chk;
case FAL_NROM_TCP_NULL_SCAN_CMD:
addr = NORM_CTRL0_ADDR;
offset = 21;
goto cmd_chk;
case FAL_NROM_TCP_SR_BLOCK_CMD:
addr = NORM_CTRL0_ADDR;
offset = 22;
goto cmd_chk;
case FAL_NROM_TCP_SF_BLOCK_CMD:
addr = NORM_CTRL0_ADDR;
offset = 23;
goto cmd_chk;
case FAL_NROM_TCP_SAR_BLOCK_CMD:
addr = NORM_CTRL0_ADDR;
offset = 24;
goto cmd_chk;
case FAL_NROM_TCP_RST_SCAN_CMD:
addr = NORM_CTRL0_ADDR;
offset = 25;
goto cmd_chk;
case FAL_NROM_TCP_SYN_WITH_DATA_CMD:
addr = NORM_CTRL0_ADDR;
offset = 26;
goto cmd_chk;
case FAL_NROM_TCP_RST_WITH_DATA_CMD:
addr = NORM_CTRL0_ADDR;
offset = 27;
goto cmd_chk;
case FAL_NROM_TCP_FA_BLOCK_CMD:
addr = NORM_CTRL0_ADDR;
offset = 28;
goto cmd_chk;
case FAL_NROM_TCP_PA_BLOCK_CMD:
addr = NORM_CTRL0_ADDR;
offset = 29;
goto cmd_chk;
case FAL_NROM_TCP_UA_BLOCK_CMD:
addr = NORM_CTRL1_ADDR;
offset = 0;
goto cmd_chk;
case FAL_NROM_TCP_INVALID_CHKSUM_CMD:
addr = NORM_CTRL1_ADDR;
offset = 1;
goto cmd_chk;
case FAL_NROM_TCP_INVALID_URGPTR_CMD:
addr = NORM_CTRL1_ADDR;
offset = 2;
goto cmd_chk;
case FAL_NROM_TCP_INVALID_OPTIONS_CMD:
addr = NORM_CTRL1_ADDR;
offset = 3;
goto cmd_chk;
case FAL_NROM_UDP_BLAT_CMD:
addr = NORM_CTRL1_ADDR;
offset = 4;
goto cmd_chk;
case FAL_NROM_UDP_INVALID_LEN_CMD:
addr = NORM_CTRL1_ADDR;
offset = 5;
goto cmd_chk;
case FAL_NROM_UDP_INVALID_CHKSUM_CMD:
addr = NORM_CTRL1_ADDR;
offset = 6;
goto cmd_chk;
case FAL_NROM_ICMP4_PING_PL_EXCEED_CMD:
addr = NORM_CTRL1_ADDR;
offset = 7;
goto cmd_chk;
case FAL_NROM_ICMP6_PING_PL_EXCEED_CMD:
addr = NORM_CTRL1_ADDR;
offset = 8;
goto cmd_chk;
case FAL_NROM_ICMP4_PING_FRAG_CMD:
addr = NORM_CTRL1_ADDR;
offset = 9;
goto cmd_chk;
case FAL_NROM_ICMP6_PING_FRAG_CMD:
addr = NORM_CTRL1_ADDR;
offset = 10;
goto cmd_chk;
case FAL_NROM_ICMP4_PING_MAX_PL_VALUE:
addr = NORM_CTRL2_ADDR;
offset = 0;
len = 14;
goto set_reg;
case FAL_NROM_ICMP6_PING_MAX_PL_VALUE:
addr = NORM_CTRL2_ADDR;
offset = 16;
len = 14;
goto set_reg;
default:
return SW_BAD_PARAM;
}
sts_chk:
if (A_TRUE == enable)
{
val = 1;
}
else if (A_FALSE == enable)
{
val = 0;
}
else
{
return SW_BAD_PARAM;
}
goto set_reg;
s_cmd_chk:
if (FAL_MAC_FRWRD == cmd)
{
val = 0;
}
else if (FAL_MAC_DROP == cmd)
{
val = 3;
}
else if (FAL_MAC_RDT_TO_CPU == cmd)
{
val = 2;
}
else
{
return SW_BAD_PARAM;
}
goto set_reg;
cmd_chk:
if (FAL_MAC_FRWRD == cmd)
{
val = 0;
}
else if (FAL_MAC_DROP == cmd)
{
val = 1;
}
else
{
return SW_BAD_PARAM;
}
set_reg:
HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
(a_uint8_t *) (®), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
SW_REG_SET_BY_FIELD_U32(reg, val, offset, len);
HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
(a_uint8_t *) (®), sizeof (a_uint32_t));
return rv;
}
