/* * --------------------- FETCH DERIVED FUNCTION */ void CaPerfTranslator::trans_ibs_fetch(struct ibs_fetch_sample* trans_fetch, gtUInt32 selected_flag, CpuProfileProcess* pProc, gtUInt64 ldAddr, gtUInt32 funcSize, CpuProfileModule* pMod, gtUInt64 ip, gtUInt32 pid, gtUInt32 tid, gtUInt32 cpu, gtUInt32 os, gtUInt32 usr, gtUInt32 count, const FunctionSymbolInfo* pFuncInfo) { // In per-process mode, ignore this sample if it does not belong to the target pid if (! _isTargetPid(pid)) { return; } if ((selected_flag) == 0) { return; } CHECK_FETCH_SELECTED_FLAG(DE_IBS_FETCH_ALL) { /* IBS all fetch samples (kills + attempts) */ AGG_IBS_COUNT(DE_IBS_FETCH_ALL, count); } CHECK_FETCH_SELECTED_FLAG(DE_IBS_FETCH_KILLED) { /* IBS killed fetches ("case 0") -- All interesting event * flags are clear */ if (IBS_FETCH_KILLED(trans_fetch)) { AGG_IBS_COUNT(DE_IBS_FETCH_KILLED, count); } } CHECK_FETCH_SELECTED_FLAG(DE_IBS_FETCH_ATTEMPTED) { /* Any non-killed fetch is an attempted fetch */ if (!IBS_FETCH_KILLED(trans_fetch)) { AGG_IBS_COUNT(DE_IBS_FETCH_ATTEMPTED, count); } } CHECK_FETCH_SELECTED_FLAG(DE_IBS_FETCH_COMPLETED) { if (!IBS_FETCH_KILLED(trans_fetch) && IBS_FETCH_FETCH_COMPLETION(trans_fetch)) /* IBS Fetch Completed */ { AGG_IBS_COUNT(DE_IBS_FETCH_COMPLETED, count); } } CHECK_FETCH_SELECTED_FLAG(DE_IBS_FETCH_ABORTED) { if (!IBS_FETCH_KILLED(trans_fetch) && !IBS_FETCH_FETCH_COMPLETION(trans_fetch)) /* IBS Fetch Aborted */ { AGG_IBS_COUNT(DE_IBS_FETCH_ABORTED, count); } } CHECK_FETCH_SELECTED_FLAG(DE_IBS_L1_ITLB_HIT) { /* IBS L1 ITLB hit */ if (IBS_FETCH_L1_TLB_HIT(trans_fetch)) { AGG_IBS_COUNT(DE_IBS_L1_ITLB_HIT, count); } } CHECK_FETCH_SELECTED_FLAG(DE_IBS_ITLB_L1M_L2H) { /* IBS L1 ITLB miss and L2 ITLB hit */ if (IBS_FETCH_ITLB_L1M_L2H(trans_fetch)) { AGG_IBS_COUNT(DE_IBS_ITLB_L1M_L2H, count); } } CHECK_FETCH_SELECTED_FLAG(DE_IBS_ITLB_L1M_L2M) { /* IBS L1 & L2 ITLB miss; complete ITLB miss */ if (IBS_FETCH_ITLB_L1M_L2M(trans_fetch)) { AGG_IBS_COUNT(DE_IBS_ITLB_L1M_L2M, count); } } CHECK_FETCH_SELECTED_FLAG(DE_IBS_IC_MISS) { /* IBS instruction cache miss */ if (IBS_FETCH_INST_CACHE_MISS(trans_fetch)) { AGG_IBS_COUNT(DE_IBS_IC_MISS, count); } } CHECK_FETCH_SELECTED_FLAG(DE_IBS_IC_HIT) { /* IBS instruction cache hit */ if (IBS_FETCH_INST_CACHE_HIT(trans_fetch)) { AGG_IBS_COUNT(DE_IBS_IC_HIT, count); } } CHECK_FETCH_SELECTED_FLAG(DE_IBS_FETCH_4K_PAGE) { if (IBS_FETCH_PHYS_ADDR_VALID(trans_fetch) && IBS_FETCH_TLB_PAGE_SIZE_4K(trans_fetch)) { AGG_IBS_COUNT(DE_IBS_FETCH_4K_PAGE, count); } } CHECK_FETCH_SELECTED_FLAG(DE_IBS_FETCH_2M_PAGE) { if (IBS_FETCH_PHYS_ADDR_VALID(trans_fetch) && IBS_FETCH_TLB_PAGE_SIZE_2M(trans_fetch)) { AGG_IBS_COUNT(DE_IBS_FETCH_2M_PAGE, count); } } CHECK_FETCH_SELECTED_FLAG(DE_IBS_FETCH_1G_PAGE) { if (IBS_FETCH_PHYS_ADDR_VALID(trans_fetch) && IBS_FETCH_TLB_PAGE_SIZE_1G(trans_fetch)) { AGG_IBS_COUNT(DE_IBS_FETCH_1G_PAGE, count); } } CHECK_FETCH_SELECTED_FLAG(DE_IBS_FETCH_XX_PAGE) { } CHECK_FETCH_SELECTED_FLAG(DE_IBS_FETCH_LATENCY) { if (IBS_FETCH_FETCH_LATENCY(trans_fetch)) AGG_IBS_COUNT(DE_IBS_FETCH_LATENCY, IBS_FETCH_FETCH_LATENCY(trans_fetch)); } }
/* * --------------------- OP DERIVED FUNCTION */ void trans_ibs_fetch (struct transient * trans, unsigned int selected_flag, unsigned int size) { struct ibs_fetch_sample * trans_fetch = ((struct ibs_sample*)(trans->ext))->fetch; unsigned int i, j, mask = 1; for (i = IBS_FETCH_BASE, j =0 ; i <= IBS_FETCH_END && j < size ; i++, mask = mask << 1) { if ((selected_flag & mask) == 0) continue; j++; switch (i) { case DE_IBS_FETCH_ALL: /* IBS all fetch samples (kills + attempts) */ AGG_IBS_EVENT(DE_IBS_FETCH_ALL); break; case DE_IBS_FETCH_KILLED: /* IBS killed fetches ("case 0") -- All interesting event * flags are clear */ if (IBS_FETCH_KILLED(trans_fetch)) AGG_IBS_EVENT(DE_IBS_FETCH_KILLED); break; case DE_IBS_FETCH_ATTEMPTED: /* Any non-killed fetch is an attempted fetch */ AGG_IBS_EVENT(DE_IBS_FETCH_ATTEMPTED); break; case DE_IBS_FETCH_COMPLETED: if (IBS_FETCH_FETCH_COMPLETION(trans_fetch)) /* IBS Fetch Completed */ AGG_IBS_EVENT(DE_IBS_FETCH_COMPLETED); break; case DE_IBS_FETCH_ABORTED: if (!IBS_FETCH_FETCH_COMPLETION(trans_fetch)) /* IBS Fetch Aborted */ AGG_IBS_EVENT(DE_IBS_FETCH_ABORTED); break; case DE_IBS_L1_ITLB_HIT: /* IBS L1 ITLB hit */ if (IBS_FETCH_L1_TLB_HIT(trans_fetch)) AGG_IBS_EVENT(DE_IBS_L1_ITLB_HIT); break; case DE_IBS_ITLB_L1M_L2H: /* IBS L1 ITLB miss and L2 ITLB hit */ if (IBS_FETCH_ITLB_L1M_L2H(trans_fetch)) AGG_IBS_EVENT(DE_IBS_ITLB_L1M_L2H); break; case DE_IBS_ITLB_L1M_L2M: /* IBS L1 & L2 ITLB miss; complete ITLB miss */ if (IBS_FETCH_ITLB_L1M_L2M(trans_fetch)) AGG_IBS_EVENT(DE_IBS_ITLB_L1M_L2M); break; case DE_IBS_IC_MISS: /* IBS instruction cache miss */ if (IBS_FETCH_INST_CACHE_MISS(trans_fetch)) AGG_IBS_EVENT(DE_IBS_IC_MISS); break; case DE_IBS_IC_HIT: /* IBS instruction cache hit */ if (IBS_FETCH_INST_CACHE_HIT(trans_fetch)) AGG_IBS_EVENT(DE_IBS_IC_HIT); break; case DE_IBS_FETCH_4K_PAGE: if (IBS_FETCH_PHYS_ADDR_VALID(trans_fetch) && IBS_FETCH_TLB_PAGE_SIZE(trans_fetch) == L1TLB4K) AGG_IBS_EVENT(DE_IBS_FETCH_4K_PAGE); break; case DE_IBS_FETCH_2M_PAGE: if (IBS_FETCH_PHYS_ADDR_VALID(trans_fetch) && IBS_FETCH_TLB_PAGE_SIZE(trans_fetch) == L1TLB2M) AGG_IBS_EVENT(DE_IBS_FETCH_2M_PAGE); break; case DE_IBS_FETCH_1G_PAGE: if (IBS_FETCH_PHYS_ADDR_VALID(trans_fetch) && IBS_FETCH_TLB_PAGE_SIZE(trans_fetch) == L1TLB1G) AGG_IBS_EVENT(DE_IBS_FETCH_1G_PAGE); break; case DE_IBS_FETCH_XX_PAGE: break; case DE_IBS_FETCH_LATENCY: if (IBS_FETCH_FETCH_LATENCY(trans_fetch)) AGG_IBS_COUNT(DE_IBS_FETCH_LATENCY, IBS_FETCH_FETCH_LATENCY(trans_fetch)); break; default: break; } } }