static inline void init_atm_tc(void)
{
IFX_REG_W32(0x00010040, SFSM_CFG0);
IFX_REG_W32(0x00010040, SFSM_CFG1);
IFX_REG_W32(0x00020000, SFSM_PGCNT0);
IFX_REG_W32(0x00020000, SFSM_PGCNT1);
IFX_REG_W32(0x00000000, DREG_AT_IDLE0);
IFX_REG_W32(0x00000000, DREG_AT_IDLE1);
IFX_REG_W32(0x00000000, DREG_AR_IDLE0);
IFX_REG_W32(0x00000000, DREG_AR_IDLE1);
IFX_REG_W32(0x0000080C, DREG_B0_LADR);
IFX_REG_W32(0x0000080C, DREG_B1_LADR);
IFX_REG_W32(0x000001F0, DREG_AR_CFG0);
IFX_REG_W32(0x000001F0, DREG_AR_CFG1);
IFX_REG_W32(0x000001E0, DREG_AT_CFG0);
IFX_REG_W32(0x000001E0, DREG_AT_CFG1);
/* clear sync state */
//IFX_REG_W32(0, SFSM_STATE0);
//IFX_REG_W32(0, SFSM_STATE1);
IFX_REG_W32_MASK(0, 1 << 14, SFSM_CFG0); // enable SFSM storing
IFX_REG_W32_MASK(0, 1 << 14, SFSM_CFG1);
IFX_REG_W32_MASK(0, 1 << 15, SFSM_CFG0); // HW keep the IDLE cells in RTHA buffer
IFX_REG_W32_MASK(0, 1 << 15, SFSM_CFG1);
IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC0);
IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC1);
IFX_REG_W32(0x00030028, FFSM_CFG0); // Force_idle
IFX_REG_W32(0x00030028, FFSM_CFG1);
}
static int ptm_napi_poll(struct napi_struct *napi, int budget)
{
int ndev;
unsigned int work_done;
for ( ndev = 0; ndev < ARRAY_SIZE(g_net_dev) && g_net_dev[ndev] != napi->dev; ndev++ );
work_done = ptm_poll(ndev, budget);
// interface down
if ( !netif_running(napi->dev) ) {
napi_complete(napi);
return work_done;
}
// no more traffic
if ( WRX_DMA_CHANNEL_CONFIG(ndev)->vlddes == 0 ) {
// clear interrupt
IFX_REG_W32_MASK(0, 1 << ndev, MBOX_IGU1_ISRC);
// double check
if ( WRX_DMA_CHANNEL_CONFIG(ndev)->vlddes == 0 ) {
napi_complete(napi);
IFX_REG_W32_MASK(0, 1 << ndev, MBOX_IGU1_IER);
return work_done;
}
}
// next round
return work_done;
}
/*
* Description:
* Halt PP32.
* Input:
* none
* Output:
* none
*/
void ifx_pp32_stop(int pp32)
{
unsigned int mask = 1 << (pp32 << 4);
/* halt PP32 */
IFX_REG_W32_MASK(0, mask, PP32_FREEZE);
}
/*
* Description:
* Download PPE firmware binary code.
* Input:
* pp32 --- int, which pp32 core
* src --- u32 *, binary code buffer
* dword_len --- unsigned int, binary code length in DWORD (32-bit)
* Output:
* int --- IFX_SUCCESS: Success
* else: Error Code
*/
static inline int pp32_download_code(int pp32, u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
{
unsigned int clr, set;
volatile u32 *dest;
if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
|| data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )
return IFX_ERROR;
clr = pp32 ? 0xF0 : 0x0F;
if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )
set = pp32 ? (3 << 6): (2 << 2);
else
set = 0x00;
IFX_REG_W32_MASK(clr, set, CDM_CFG);
/* copy code */
dest = CDM_CODE_MEMORY(pp32, 0);
while ( code_dword_len-- > 0 )
IFX_REG_W32(*code_src++, dest++);
/* copy data */
dest = CDM_DATA_MEMORY(pp32, 0);
while ( data_dword_len-- > 0 )
IFX_REG_W32(*data_src++, dest++);
return IFX_SUCCESS;
}
/*!
\fn void ifx_rcu_rst_req_write(unsigned int value, unsigned int mask)
\brief Write register "IFX_RCU_RST_REQ" to reset individual hardware module.
This function provide direct access to register "IFX_RCU_RST_REQ" for
reseting individual hardware module. Protection for multiple access
is provided in this function.
\param value - unsigned int, each bit stands for one hardware module
\param mask - usnigned int, value AND mask before writing to register
\ingroup IFX_RCU_API
*/
void ifx_rcu_rst_req_write(unsigned int value, unsigned int mask)
{
unsigned long sys_flags;
spin_lock_irqsave(&g_rcu_register_lock, sys_flags);
IFX_REG_W32_MASK(mask, value & mask, IFX_RCU_RST_REQ);
spin_unlock_irqrestore(&g_rcu_register_lock, sys_flags);
}
/*!
\fn void ifx_nand_select_chip(struct mtd_info *mtd, int chip)
\ingroup IFX_NAND_DRV
\brief control CE line
\param mtd MTD device structure
\param chipnumber to select, -1 for deselect
\return none
*/
static void ifx_nand_select_chip(struct mtd_info *mtd, int chip)
{
struct nand_chip *nand = mtd->priv;
switch (chip) {
case -1:
NAND_DISABLE_CE(nand);
IFX_REG_W32_MASK(IFX_EBU_NAND_CON_NANDM, 0, IFX_EBU_NAND_CON);
break;
case 0:
IFX_REG_W32_MASK(0, IFX_EBU_NAND_CON_NANDM, IFX_EBU_NAND_CON);
NAND_ENABLE_CE(nand);
#if 0 // ctc
// NAND_WRITE(NAND_WRITE_CMD, NAND_WRITE_CMD_RESET); // Reset nand chip // Jess Refer from Lantiq (Remove It.)
#endif
break;
default:
BUG();
}
}
static void ptm_tx_timeout(struct net_device *dev)
{
int ndev;
for ( ndev = 0; ndev < ARRAY_SIZE(g_net_dev) && g_net_dev[ndev] != dev; ndev++ );
ASSERT(ndev >= 0 && ndev < ARRAY_SIZE(g_net_dev), "ndev = %d (wrong value)", ndev);
/* disable TX irq, release skb when sending new packet */
IFX_REG_W32_MASK(1 << (ndev + 16), 0, MBOX_IGU1_IER);
/* wake up TX queue */
netif_wake_queue(dev);
return;
}
static int ptm_stop(struct net_device *dev)
{
int ndev;
for ( ndev = 0; ndev < ARRAY_SIZE(g_net_dev) && g_net_dev[ndev] != dev; ndev++ );
ASSERT(ndev >= 0 && ndev < ARRAY_SIZE(g_net_dev), "ndev = %d (wrong value)", ndev);
IFX_REG_W32_MASK((1 << ndev) | (1 << (ndev + 16)), 0, MBOX_IGU1_IER);
napi_disable(&g_ptm_priv_data.itf[ndev].napi);
netif_stop_queue(dev);
return 0;
}
/*
* Description:
* Initialize and start up PP32.
* Input:
* none
* Output:
* int --- IFX_SUCCESS: Success
* else: Error Code
*/
int ifx_pp32_start(int pp32)
{
unsigned int mask = 1 << (pp32 << 4);
int ret;
/* download firmware */
ret = pp32_download_code(pp32, firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data));
if ( ret != IFX_SUCCESS )
return ret;
/* run PP32 */
IFX_REG_W32_MASK(mask, 0, PP32_FREEZE);
/* idle for a while to let PP32 init itself */
udelay(10);
return IFX_SUCCESS;
}
static int ptm_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
{
int ndev;
unsigned int f_full;
int desc_base;
register struct tx_descriptor reg_desc = {0};
for ( ndev = 0; ndev < ARRAY_SIZE(g_net_dev) && g_net_dev[ndev] != dev; ndev++ );
ASSERT(ndev >= 0 && ndev < ARRAY_SIZE(g_net_dev), "ndev = %d (wrong value)", ndev);
if ( !g_showtime ) {
err("not in showtime");
goto PTM_HARD_START_XMIT_FAIL;
}
/* allocate descriptor */
desc_base = get_tx_desc(ndev, &f_full);
if ( f_full ) {
dev->trans_start = jiffies;
netif_stop_queue(dev);
IFX_REG_W32_MASK(0, 1 << (ndev + 16), MBOX_IGU1_ISRC);
IFX_REG_W32_MASK(0, 1 << (ndev + 16), MBOX_IGU1_IER);
}
if ( desc_base < 0 )
goto PTM_HARD_START_XMIT_FAIL;
if ( g_ptm_priv_data.itf[ndev].tx_skb[desc_base] != NULL )
dev_kfree_skb_any(g_ptm_priv_data.itf[ndev].tx_skb[desc_base]);
g_ptm_priv_data.itf[ndev].tx_skb[desc_base] = skb;
reg_desc.dataptr = (unsigned int)skb->data >> 2;
reg_desc.datalen = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
reg_desc.byteoff = (unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1);
reg_desc.own = 1;
reg_desc.c = 1;
reg_desc.sop = reg_desc.eop = 1;
/* write discriptor to memory and write back cache */
g_ptm_priv_data.itf[ndev].tx_desc[desc_base] = reg_desc;
dma_cache_wback((unsigned long)skb->data, skb->len);
wmb();
dump_skb(skb, DUMP_SKB_LEN, (char *)__func__, ndev, ndev, 1);
if ( (ifx_ptm_dbg_enable & DBG_ENABLE_MASK_MAC_SWAP) ) {
skb_swap(skb);
}
g_ptm_priv_data.itf[ndev].stats.tx_packets++;
g_ptm_priv_data.itf[ndev].stats.tx_bytes += reg_desc.datalen;
dev->trans_start = jiffies;
mailbox_signal(ndev, 1);
adsl_led_flash();
return NETDEV_TX_OK;
PTM_HARD_START_XMIT_FAIL:
dev_kfree_skb_any(skb);
g_ptm_priv_data.itf[ndev].stats.tx_dropped++;
return NETDEV_TX_OK;
}
static inline void NAND_ENABLE_CE(struct nand_chip *nand) { IFX_REG_W32_MASK(0,NAND_CON_CE,IFX_EBU_NAND_CON); }
