&apb1_interface, &apb2_interface, &evt1_module_1_interface, &evt1_module_2_interface, &evt1_module_3A_interface, &evt1_module_3B_interface, &evt1_module_4A_interface, &evt1_module_4B_interface, &evt1_module_5_lcd_interface, }; /* * EVT1.5 interface ports */ static struct vreg_data evt1_5_module_1_vreg_data[] = { INIT_ACTIVE_HIGH_VREG_DATA(VSYS_EN1_N, HOLD_TIME_MODULE), INIT_MODULE_CLK_DATA(REFCLK_1_EN), }; static struct vreg_data evt1_5_module_2_vreg_data[] = { INIT_ACTIVE_HIGH_VREG_DATA(VSYS_EN2_N, HOLD_TIME_MODULE), INIT_MODULE_CLK_DATA(REFCLK_2_EN), }; static struct vreg_data evt1_5_module_3A_vreg_data[] = { INIT_ACTIVE_HIGH_VREG_DATA(VSYS_EN3A_N, HOLD_TIME_MODULE), INIT_MODULE_CLK_DATA(REFCLK_3A_EN), }; static struct vreg_data evt1_5_module_3B_vreg_data[] = { INIT_ACTIVE_HIGH_VREG_DATA(VSYS_EN3B_N, HOLD_TIME_MODULE),
/* Bootret pins: active low, enabled by default */ #define INIT_BOOTRET_DATA(g) \ { \ .gpio = g, \ .hold_time = 0, \ .active_high = 0, \ .def_val = 0, \ } /* * Built-in bridge voltage regulator list */ static struct vreg_data apb1_vreg_data[] = { INIT_BOOTRET_DATA(BOOTRET_APB1), INIT_ACTIVE_HIGH_VREG_DATA(STM32_GPIO_PIN(GPIO_PORTD | GPIO_PIN4), HOLD_TIME_1P1), INIT_ACTIVE_HIGH_VREG_DATA(STM32_GPIO_PIN(GPIO_PORTD | GPIO_PIN6), HOLD_TIME_1P8), INIT_ACTIVE_HIGH_VREG_DATA(STM32_GPIO_PIN(GPIO_PORTD | GPIO_PIN5), HOLD_TIME_1P2), INIT_SVC_RST_DATA(SVC_RST_APB1), }; static struct vreg_data apb2_vreg_data[] = { INIT_BOOTRET_DATA(BOOTRET_APB2), INIT_ACTIVE_HIGH_VREG_DATA(STM32_GPIO_PIN(GPIO_PORTD | GPIO_PIN11), HOLD_TIME_1P1), INIT_ACTIVE_HIGH_VREG_DATA(STM32_GPIO_PIN(GPIO_PORTD | GPIO_PIN10), HOLD_TIME_1P8), INIT_ACTIVE_HIGH_VREG_DATA(STM32_GPIO_PIN(GPIO_PORTE | GPIO_PIN7), HOLD_TIME_1P2),
&apb2_interface, &module_1_interface, &module_2_interface, &module_3A_interface, &module_3B_interface, &module_4A_interface, &module_4B_interface, &module_5_lcd_interface, }; /* * UniPro Switch vreg */ static struct vreg_data sw_vreg_data[] = { INIT_ACTIVE_HIGH_VREG_DATA(SW_1P1_EN, HOLD_TIME_SW_1P1), /* * HACK: put the 1.8V power supplies into PWM mode always. * * TODO [SW-1934] investigate methods for allowing supply to * alternate between PWM/PFM modes automatically without * causing voltage droops observed in DB3 bringup. */ INIT_ACTIVE_HIGH_VREG_DATA(SW_UNIPRO_1P8_PWM, 0), INIT_ACTIVE_HIGH_VREG_DATA(SW_IO_1P8_PWM, 0), /* END HACK */ INIT_ACTIVE_HIGH_VREG_DATA(SW_1P8_IO_EN, 0), INIT_ACTIVE_HIGH_VREG_DATA(SW_1P8_UNIPRO_EN, HOLD_TIME_SW_1P8), INIT_ACTIVE_HIGH_VREG_DATA(REFCLK_SW_EN, HOLD_TIME_SW_CLK_US),