static void clk_32k_dummy(struct clk *clk) { } static const struct clkops clk_32k_dummy_ops = { .enable = clk_32k_dummy, .disable = clk_32k_dummy, }; static struct clk tmio_dummy_clk = { .ops = &clk_32k_dummy_ops, .rate = 32768, }; static struct clk_lookup eseries_clkregs[] = { INIT_CLKREG(&tmio_dummy_clk, NULL, "CLK_CK32K"), }; void eseries_register_clks(void) { clkdev_add_table(eseries_clkregs, ARRAY_SIZE(eseries_clkregs)); } #ifdef CONFIG_MACH_E330 /* -------------------- e330 tc6387xb parameters -------------------- */ static struct tc6387xb_platform_data e330_tc6387xb_info = { .enable = &eseries_tmio_enable, .disable = &eseries_tmio_disable, .suspend = &eseries_tmio_suspend, .resume = &eseries_tmio_resume,
static APBC_CLK(uart2, PXA910_UART1, 1, 14745600); static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000); static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000); static APBC_CLK(pwm1, PXA910_PWM1, 1, 13000000); static APBC_CLK(pwm2, PXA910_PWM2, 1, 13000000); static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000); static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000); static APBC_CLK(gpio, PXA910_GPIO, 0, 13000000); static APBC_CLK(rtc, PXA910_RTC, 8, 32768); static APMU_CLK(nand, NAND, 0x19b, 156000000); static APMU_CLK(u2o, USB, 0x1b, 480000000); /* device and clock bindings */ static struct clk_lookup pxa910_clkregs[] = { INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL), INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL), INIT_CLKREG(&clk_pwm1, "pxa910-pwm.0", NULL), INIT_CLKREG(&clk_pwm2, "pxa910-pwm.1", NULL), INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL), INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL), INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL), INIT_CLKREG(&clk_u2o, "pxa-u2o", "U2OCLK"), INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL), }; static int __init pxa910_init(void) {
static DEFINE_CK(pxa95x_lcd, LCD, &clk_pxa3xx_hsio_ops); static DEFINE_CLK(pxa95x_pout, &clk_pxa3xx_pout_ops, 13000000, 70); static DEFINE_PXA3_CKEN(pxa95x_ffuart, FFUART, 14857000, 1); static DEFINE_PXA3_CKEN(pxa95x_btuart, BTUART, 14857000, 1); static DEFINE_PXA3_CKEN(pxa95x_stuart, STUART, 14857000, 1); static DEFINE_PXA3_CKEN(pxa95x_i2c, I2C, 32842000, 0); static DEFINE_PXA3_CKEN(pxa95x_keypad, KEYPAD, 32768, 0); static DEFINE_PXA3_CKEN(pxa95x_ssp1, SSP1, 13000000, 0); static DEFINE_PXA3_CKEN(pxa95x_ssp2, SSP2, 13000000, 0); static DEFINE_PXA3_CKEN(pxa95x_ssp3, SSP3, 13000000, 0); static DEFINE_PXA3_CKEN(pxa95x_ssp4, SSP4, 13000000, 0); static DEFINE_PXA3_CKEN(pxa95x_pwm0, PWM0, 13000000, 0); static DEFINE_PXA3_CKEN(pxa95x_pwm1, PWM1, 13000000, 0); static struct clk_lookup pxa95x_clkregs[] = { INIT_CLKREG(&clk_pxa95x_pout, NULL, "CLK_POUT"), /* Power I2C clock is always on */ INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL), INIT_CLKREG(&clk_pxa95x_lcd, "pxa2xx-fb", NULL), INIT_CLKREG(&clk_pxa95x_ffuart, "pxa2xx-uart.0", NULL), INIT_CLKREG(&clk_pxa95x_btuart, "pxa2xx-uart.1", NULL), INIT_CLKREG(&clk_pxa95x_stuart, "pxa2xx-uart.2", NULL), INIT_CLKREG(&clk_pxa95x_stuart, "pxa2xx-ir", "UARTCLK"), INIT_CLKREG(&clk_pxa95x_i2c, "pxa2xx-i2c.0", NULL), INIT_CLKREG(&clk_pxa95x_keypad, "pxa27x-keypad", NULL), INIT_CLKREG(&clk_pxa95x_ssp1, "pxa27x-ssp.0", NULL), INIT_CLKREG(&clk_pxa95x_ssp2, "pxa27x-ssp.1", NULL), INIT_CLKREG(&clk_pxa95x_ssp3, "pxa27x-ssp.2", NULL), INIT_CLKREG(&clk_pxa95x_ssp4, "pxa27x-ssp.3", NULL), INIT_CLKREG(&clk_pxa95x_pwm0, "pxa27x-pwm.0", NULL), INIT_CLKREG(&clk_pxa95x_pwm1, "pxa27x-pwm.1", NULL),
static APBC_CLK(uart4, MMP2_UART4, 1, 26000000); static APBC_CLK(twsi1, MMP2_TWSI1, 0, 26000000); static APBC_CLK(twsi2, MMP2_TWSI2, 0, 26000000); static APBC_CLK(twsi3, MMP2_TWSI3, 0, 26000000); static APBC_CLK(twsi4, MMP2_TWSI4, 0, 26000000); static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000); static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000); static APMU_CLK(nand, NAND, 0xbf, 100000000); static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops); static APMU_CLK_OPS(sdh1, SDH1, 0x1b, 200000000, &sdhc_clk_ops); static APMU_CLK_OPS(sdh2, SDH2, 0x1b, 200000000, &sdhc_clk_ops); static APMU_CLK_OPS(sdh3, SDH3, 0x1b, 200000000, &sdhc_clk_ops); static struct clk_lookup mmp2_clkregs[] = { INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL), INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL), INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL), INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL), INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL), INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL), INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL), INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL), INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"), INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"), INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"), INIT_CLKREG(&clk_sdh3, "sdhci-pxav3.3", "PXA-SDHCLK"), };