/**
* \brief Set up a memory region.
*/
static void _setup_memory_region( void )
{
uint32_t dw_region_base_addr;
uint32_t dw_region_attr;
__DMB();
/**
* ITCM memory region --- Normal
* START_Addr:- 0x00000000UL
* END_Addr:- 0x00400000UL
*/
dw_region_base_addr =
ITCM_START_ADDRESS |
MPU_REGION_VALID |
MPU_DEFAULT_ITCM_REGION;
dw_region_attr =
MPU_AP_PRIVILEGED_READ_WRITE |
mpu_cal_mpu_region_size(ITCM_END_ADDRESS - ITCM_START_ADDRESS) |
MPU_REGION_ENABLE;
mpu_set_region( dw_region_base_addr, dw_region_attr);
/**
* Internal flash memory region --- Normal read-only
* (update to Strongly ordered in write accesses)
* START_Addr:- 0x00400000UL
* END_Addr:- 0x00600000UL
*/
dw_region_base_addr =
IFLASH_START_ADDRESS |
MPU_REGION_VALID |
MPU_DEFAULT_IFLASH_REGION;
dw_region_attr =
MPU_AP_READONLY |
INNER_NORMAL_WB_NWA_TYPE( NON_SHAREABLE ) |
mpu_cal_mpu_region_size(IFLASH_END_ADDRESS - IFLASH_START_ADDRESS) |
MPU_REGION_ENABLE;
mpu_set_region( dw_region_base_addr, dw_region_attr);
/**
* DTCM memory region --- Normal
* START_Addr:- 0x20000000L
* END_Addr:- 0x20400000UL
*/
/* DTCM memory region */
dw_region_base_addr =
DTCM_START_ADDRESS |
MPU_REGION_VALID |
MPU_DEFAULT_DTCM_REGION;
dw_region_attr =
MPU_AP_PRIVILEGED_READ_WRITE |
mpu_cal_mpu_region_size(DTCM_END_ADDRESS - DTCM_START_ADDRESS) |
MPU_REGION_ENABLE;
mpu_set_region( dw_region_base_addr, dw_region_attr);
/**
* SRAM Cacheable memory region --- Normal
* START_Addr:- 0x20400000UL
* END_Addr:- 0x2043FFFFUL
*/
/* SRAM memory region */
dw_region_base_addr =
SRAM_FIRST_START_ADDRESS |
MPU_REGION_VALID |
MPU_DEFAULT_SRAM_REGION_1;
dw_region_attr =
MPU_AP_FULL_ACCESS |
INNER_NORMAL_WB_NWA_TYPE( NON_SHAREABLE ) |
mpu_cal_mpu_region_size(SRAM_FIRST_END_ADDRESS - SRAM_FIRST_START_ADDRESS)
| MPU_REGION_ENABLE;
mpu_set_region( dw_region_base_addr, dw_region_attr);
/**
* Internal SRAM second partition memory region --- Normal
* START_Addr:- 0x20440000UL
* END_Addr:- 0x2045FFFFUL
*/
/* SRAM memory region */
dw_region_base_addr =
SRAM_SECOND_START_ADDRESS |
MPU_REGION_VALID |
MPU_DEFAULT_SRAM_REGION_2;
dw_region_attr =
MPU_AP_FULL_ACCESS |
INNER_NORMAL_WB_NWA_TYPE( NON_SHAREABLE ) |
mpu_cal_mpu_region_size(SRAM_SECOND_END_ADDRESS - SRAM_SECOND_START_ADDRESS) |
MPU_REGION_ENABLE;
mpu_set_region( dw_region_base_addr, dw_region_attr);
#ifdef MPU_HAS_NOCACHE_REGION
dw_region_base_addr =
SRAM_NOCACHE_START_ADDRESS |
MPU_REGION_VALID |
MPU_NOCACHE_SRAM_REGION;
dw_region_attr =
MPU_AP_FULL_ACCESS |
INNER_OUTER_NORMAL_NOCACHE_TYPE( SHAREABLE ) |
mpu_cal_mpu_region_size(NOCACHE_SRAM_REGION_SIZE) |
MPU_REGION_ENABLE;
mpu_set_region( dw_region_base_addr, dw_region_attr);
#endif
/**
* Peripheral memory region --- DEVICE Shareable
* START_Addr:- 0x40000000UL
* END_Addr:- 0x5FFFFFFFUL
*/
dw_region_base_addr =
PERIPHERALS_START_ADDRESS |
MPU_REGION_VALID |
MPU_PERIPHERALS_REGION;
dw_region_attr = MPU_AP_FULL_ACCESS |
MPU_REGION_EXECUTE_NEVER |
SHAREABLE_DEVICE_TYPE |
mpu_cal_mpu_region_size(PERIPHERALS_END_ADDRESS - PERIPHERALS_START_ADDRESS)
|MPU_REGION_ENABLE;
mpu_set_region( dw_region_base_addr, dw_region_attr);
/**
* External EBI memory memory region --- Strongly Ordered
* START_Addr:- 0x60000000UL
* END_Addr:- 0x6FFFFFFFUL
*/
dw_region_base_addr =
EXT_EBI_START_ADDRESS |
MPU_REGION_VALID |
MPU_EXT_EBI_REGION;
dw_region_attr =
MPU_AP_FULL_ACCESS |
/* External memory Must be defined with 'Device' or 'Strongly Ordered' attribute for write accesses (AXI) */
STRONGLY_ORDERED_SHAREABLE_TYPE |
mpu_cal_mpu_region_size(EXT_EBI_END_ADDRESS - EXT_EBI_START_ADDRESS) |
MPU_REGION_ENABLE;
mpu_set_region( dw_region_base_addr, dw_region_attr);
/**
* SDRAM cacheable memory region --- Normal
* START_Addr:- 0x70000000UL
* END_Addr:- 0x7FFFFFFFUL
*/
dw_region_base_addr =
SDRAM_START_ADDRESS |
MPU_REGION_VALID |
MPU_DEFAULT_SDRAM_REGION;
dw_region_attr =
MPU_AP_FULL_ACCESS |
INNER_NORMAL_WB_RWA_TYPE( SHAREABLE ) |
mpu_cal_mpu_region_size(SDRAM_END_ADDRESS - SDRAM_START_ADDRESS) |
MPU_REGION_ENABLE;
mpu_set_region( dw_region_base_addr, dw_region_attr);
/**
* QSPI memory region --- Strongly ordered
* START_Addr:- 0x80000000UL
* END_Addr:- 0x9FFFFFFFUL
*/
dw_region_base_addr =
QSPI_START_ADDRESS |
MPU_REGION_VALID |
MPU_QSPIMEM_REGION;
dw_region_attr =
MPU_AP_FULL_ACCESS |
STRONGLY_ORDERED_SHAREABLE_TYPE |
mpu_cal_mpu_region_size(QSPI_END_ADDRESS - QSPI_START_ADDRESS) |
MPU_REGION_ENABLE;
mpu_set_region( dw_region_base_addr, dw_region_attr);
/**
* USB RAM Memory region --- Device
* START_Addr:- 0xA0100000UL
* END_Addr:- 0xA01FFFFFUL
*/
dw_region_base_addr =
USBHSRAM_START_ADDRESS |
MPU_REGION_VALID |
MPU_USBHSRAM_REGION;
dw_region_attr =
MPU_AP_FULL_ACCESS |
MPU_REGION_EXECUTE_NEVER |
SHAREABLE_DEVICE_TYPE |
mpu_cal_mpu_region_size(USBHSRAM_END_ADDRESS - USBHSRAM_START_ADDRESS) |
MPU_REGION_ENABLE;
mpu_set_region( dw_region_base_addr, dw_region_attr);
/* Enable the memory management fault , Bus Fault, Usage Fault exception */
SCB->SHCSR |= (SCB_SHCSR_MEMFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk
| SCB_SHCSR_USGFAULTENA_Msk);
/* Enable the MPU region */
mpu_enable( MPU_ENABLE | MPU_PRIVDEFENA);
__DSB();
__ISB();
}
/**
* \brief Set up a memory region.
*/
void _SetupMemoryRegion( void )
{
uint32_t dwRegionBaseAddr;
uint32_t dwRegionAttr;
memory_barrier();
/***************************************************
ITCM memory region --- Normal
START_Addr:- 0x00000000UL
END_Addr:- 0x00400000UL
****************************************************/
dwRegionBaseAddr =
ITCM_START_ADDRESS |
MPU_REGION_VALID |
MPU_DEFAULT_ITCM_REGION; // 1
dwRegionAttr =
MPU_AP_PRIVILEGED_READ_WRITE |
MPU_CalMPURegionSize(ITCM_END_ADDRESS - ITCM_START_ADDRESS) |
MPU_REGION_ENABLE;
MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
/****************************************************
Internal flash memory region --- Normal read-only
(update to Strongly ordered in write accesses)
START_Addr:- 0x00400000UL
END_Addr:- 0x00600000UL
******************************************************/
dwRegionBaseAddr =
IFLASH_START_ADDRESS |
MPU_REGION_VALID |
MPU_DEFAULT_IFLASH_REGION; //2
dwRegionAttr =
MPU_AP_READONLY |
INNER_NORMAL_WB_NWA_TYPE( NON_SHAREABLE ) |
MPU_CalMPURegionSize(IFLASH_END_ADDRESS - IFLASH_START_ADDRESS) |
MPU_REGION_ENABLE;
MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
/****************************************************
DTCM memory region --- Normal
START_Addr:- 0x20000000L
END_Addr:- 0x20400000UL
******************************************************/
/* DTCM memory region */
dwRegionBaseAddr =
DTCM_START_ADDRESS |
MPU_REGION_VALID |
MPU_DEFAULT_DTCM_REGION; //3
dwRegionAttr =
MPU_AP_PRIVILEGED_READ_WRITE |
MPU_CalMPURegionSize(DTCM_END_ADDRESS - DTCM_START_ADDRESS) |
MPU_REGION_ENABLE;
MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
/****************************************************
SRAM Cacheable memory region --- Normal
START_Addr:- 0x20400000UL
END_Addr:- 0x2043FFFFUL
******************************************************/
/* SRAM memory region */
dwRegionBaseAddr =
SRAM_FIRST_START_ADDRESS |
MPU_REGION_VALID |
MPU_DEFAULT_SRAM_REGION_1; //4
dwRegionAttr =
MPU_AP_FULL_ACCESS |
INNER_NORMAL_WB_NWA_TYPE( NON_SHAREABLE ) |
MPU_CalMPURegionSize(SRAM_FIRST_END_ADDRESS - SRAM_FIRST_START_ADDRESS)
| MPU_REGION_ENABLE;
MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
/****************************************************
Internal SRAM second partition memory region --- Normal
START_Addr:- 0x20440000UL
END_Addr:- 0x2045FFFFUL
******************************************************/
/* SRAM memory region */
dwRegionBaseAddr =
SRAM_SECOND_START_ADDRESS |
MPU_REGION_VALID |
MPU_DEFAULT_SRAM_REGION_2; //5
dwRegionAttr =
MPU_AP_FULL_ACCESS |
INNER_NORMAL_WB_NWA_TYPE( NON_SHAREABLE ) |
MPU_CalMPURegionSize(SRAM_SECOND_END_ADDRESS - SRAM_SECOND_START_ADDRESS) |
MPU_REGION_ENABLE;
MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
/* NOCACHE_REGION */
dwRegionBaseAddr =
SRAM_NOCACHE_START_ADDRESS |
MPU_REGION_VALID |
MPU_NOCACHE_SRAM_REGION; //11
dwRegionAttr =
MPU_AP_FULL_ACCESS |
INNER_OUTER_NORMAL_NOCACHE_TYPE( SHAREABLE ) |
MPU_CalMPURegionSize(NOCACHE_SRAM_REGION_SIZE) |
MPU_REGION_ENABLE;
MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
/****************************************************
Peripheral memory region --- DEVICE Shareable
START_Addr:- 0x40000000UL
END_Addr:- 0x5FFFFFFFUL
******************************************************/
dwRegionBaseAddr =
PERIPHERALS_START_ADDRESS |
MPU_REGION_VALID |
MPU_PERIPHERALS_REGION; //6
dwRegionAttr = MPU_AP_FULL_ACCESS |
MPU_REGION_EXECUTE_NEVER |
SHAREABLE_DEVICE_TYPE |
MPU_CalMPURegionSize(PERIPHERALS_END_ADDRESS - PERIPHERALS_START_ADDRESS)
|MPU_REGION_ENABLE;
MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
/****************************************************
External EBI memory memory region --- Strongly Ordered
START_Addr:- 0x60000000UL
END_Addr:- 0x6FFFFFFFUL
******************************************************/
dwRegionBaseAddr =
EXT_EBI_START_ADDRESS |
MPU_REGION_VALID |
MPU_EXT_EBI_REGION; //7
dwRegionAttr =
MPU_AP_FULL_ACCESS |
/* External memory Must be defined with 'Device' or 'Strongly Ordered'
attribute for write accesses (AXI) */
STRONGLY_ORDERED_SHAREABLE_TYPE |
MPU_CalMPURegionSize(EXT_EBI_END_ADDRESS - EXT_EBI_START_ADDRESS) |
MPU_REGION_ENABLE;
MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
/****************************************************
SDRAM Cacheable memory region --- Normal
START_Addr:- 0x70000000UL
END_Addr:- 0x7FFFFFFFUL
******************************************************/
dwRegionBaseAddr =
SDRAM_START_ADDRESS |
MPU_REGION_VALID |
MPU_DEFAULT_SDRAM_REGION; //8
dwRegionAttr =
MPU_AP_FULL_ACCESS |
INNER_NORMAL_WB_RWA_TYPE( SHAREABLE ) |
MPU_CalMPURegionSize(SDRAM_END_ADDRESS - SDRAM_START_ADDRESS) |
MPU_REGION_ENABLE;
MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
/****************************************************
QSPI memory region --- Strongly ordered
START_Addr:- 0x80000000UL
END_Addr:- 0x9FFFFFFFUL
******************************************************/
dwRegionBaseAddr =
QSPI_START_ADDRESS |
MPU_REGION_VALID |
MPU_QSPIMEM_REGION; //9
dwRegionAttr =
MPU_AP_FULL_ACCESS |
STRONGLY_ORDERED_SHAREABLE_TYPE |
MPU_CalMPURegionSize(QSPI_END_ADDRESS - QSPI_START_ADDRESS) |
MPU_REGION_ENABLE;
MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
/****************************************************
USB RAM Memory region --- Device
START_Addr:- 0xA0100000UL
END_Addr:- 0xA01FFFFFUL
******************************************************/
dwRegionBaseAddr =
USBHSRAM_START_ADDRESS |
MPU_REGION_VALID |
MPU_USBHSRAM_REGION; //10
dwRegionAttr =
MPU_AP_FULL_ACCESS |
MPU_REGION_EXECUTE_NEVER |
SHAREABLE_DEVICE_TYPE |
MPU_CalMPURegionSize(USBHSRAM_END_ADDRESS - USBHSRAM_START_ADDRESS) |
MPU_REGION_ENABLE;
MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
/* Enable the memory management fault , Bus Fault, Usage Fault exception */
SCB->SHCSR |= (SCB_SHCSR_MEMFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk
| SCB_SHCSR_USGFAULTENA_Msk);
/* Enable the MPU region */
MPU_Enable( MPU_ENABLE | MPU_PRIVDEFENA);
memory_sync();
}
