FLCTL, SDHI0 } }, { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, MSU_MSU, IIC1 } }, { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2, SIU, TTI20 } }, { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_CMT13, IREM, SDHI1 } }, { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, TPU1, TPU2, TPU3 } }, { 0xe6940030, 0, 16, 4, /* IPRMA */ { MISTY, CMT3, RWDT1, RWDT0 } }, { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, SPU, DDM } }, { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } }, }; static struct intc_desc intca_desc __initdata = { .name = "sh7367-intca", .force_enable = ENABLED, .force_disable = DISABLED, .hw = INTC_HW_DESC(intca_vectors, intca_groups, intca_mask_registers, intca_prio_registers, NULL, NULL), }; INTC_IRQ_PINS_16(intca_irq_pins, 0xe6900000, INTC_VECT, "sh7367-intca-irq-pins"); enum { UNUSED_INTCS = 0, INTCS, /* interrupt sources INTCS */ VIO2_VEU0, VIO2_VEU1, VIO2_VEU2, VIO2_VEU3, VIO3_VOU, RTDMAC_1_DEI0, RTDMAC_1_DEI1, RTDMAC_1_DEI2, RTDMAC_1_DEI3,
{ 0xa4080020, 0, 16, 4, { SIO, 0, TSIF, I2C1 } }, { 0xa4080024, 0, 16, 4, { Z3D4, 0, SIU } }, { 0xa4080028, 0, 16, 4, { 0, MMC, 0, SDHI } }, { 0xa408002c, 0, 16, 4, { 0, 0, TPU } }, { 0xa4140010, 0, 32, 4, { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, }; static struct intc_sense_reg sense_registers[] __initdata = { { 0xa414001c, 16, 2, { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, }; static struct intc_mask_reg ack_registers[] __initdata = { { 0xa4140024, 0, 8, { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, }; static struct intc_desc intc_desc __initdata = { .name = "sh7343", .force_enable = ENABLED, .force_disable = DISABLED, .hw = INTC_HW_DESC(vectors, groups, mask_registers, prio_registers, sense_registers, ack_registers), }; void __init plat_irq_setup(void) { register_intc_controller(&intc_desc); }