void CPUCALL ia32_interrupt(int vect, int soft) { // TRACEOUT(("int (%x, %x) PE=%d VM=%d", vect, soft, CPU_STAT_PM, CPU_STAT_VM86)); if (!soft) { INTERRUPT(vect, FALSE, FALSE, 0); } else { if (CPU_STAT_VM86 && (CPU_STAT_IOPL < CPU_IOPL3) && (soft == -1)) { TRACEOUT(("BIOS interrupt: VM86 && IOPL < 3 && INTn")); } INTERRUPT(vect, TRUE, FALSE, 0); } }
void CPUCALL ia32_interrupt(int vect, int soft) { // TRACEOUT(("int (%x, %x) PE=%d VM=%d", vect, soft, CPU_STAT_PM, CPU_STAT_VM86)); if (!soft) { INTERRUPT(vect, INTR_TYPE_EXTINTR); } else { if (CPU_STAT_PM && CPU_STAT_VM86 && CPU_STAT_IOPL < CPU_IOPL3) { VERBOSE(("ia32_interrupt: VM86 && IOPL < 3 && INTn")); EXCEPTION(GP_EXCEPTION, 0); } INTERRUPT(vect, INTR_TYPE_SOFTINTR); } }
void INT3(void) { CPU_WORKCLOCK(33); INTERRUPT(3, INTR_TYPE_SOFTINTR); }
UINT8 ia32_step(void) { int rv; rv = sigsetjmp(exec_1step_jmpbuf, 1); switch (rv) { case 0: break; case 1: VERBOSE(("ia32_step: return from exception")); break; case 2: VERBOSE(("ia32_step: return from panic")); return FALSE; default: VERBOSE(("ia32_step: return from unknown cause")); break; } // do { exec_1step(); if (CPU_TRAP) { CPU_DR6 |= CPU_DR6_BS; INTERRUPT(1, INTR_TYPE_EXCEPTION); } if (dmac.working) { dmax86(); } // } while (CPU_REMCLOCK > 0); return TRUE; }
void DOSCALL() // DOSCALL { Push(Read16(cc_AX) + 1); // AX 1+ C_ex__2(); // C!_2 Push(0x0021); INTERRUPT(); // INTERRUPT }
void W451A() // W451A { Push(0x0011); INTERRUPT(); // INTERRUPT Push(Read16(Read16(cc_AX)) & 0x00c0); // AX @ 0x00c0 AND Push(0x0040); _slash_(); // / Push(Pop() + 1); // 1+ }
void INTO(void) { if (!CPU_OV) { CPU_WORKCLOCK(3); return; } CPU_WORKCLOCK(35); INTERRUPT(4, INTR_TYPE_SOFTINTR); }
void ia32(void) { int rv; rv = sigsetjmp(exec_1step_jmpbuf, 1); switch (rv) { case 0: break; case 1: VERBOSE(("ia32: return from exception")); break; case 2: VERBOSE(("ia32: return from panic")); return; default: VERBOSE(("ia32: return from unknown cause")); break; } #if defined(IA32_SUPPORT_DEBUG_REGISTER) do { exec_1step(); if (dmac.working) { dmax86(); } } while (CPU_REMCLOCK > 0); #else if (CPU_TRAP) { do { exec_1step(); if (CPU_TRAP) { CPU_DR6 |= CPU_DR6_BS; INTERRUPT(1, TRUE, FALSE, 0); } dmax86(); } while (CPU_REMCLOCK > 0); } else if (dmac.working) { do { exec_1step(); dmax86(); } while (CPU_REMCLOCK > 0); } else { do { exec_1step(); } while (CPU_REMCLOCK > 0); } #endif }
void INT_Ib(void) { UINT8 vect; CPU_WORKCLOCK(37); if (!CPU_STAT_PM || !CPU_STAT_VM86 || (CPU_STAT_IOPL == CPU_IOPL3)) { GET_PCBYTE(vect); #if defined(ENABLE_TRAP) softinttrap(CPU_CS, CPU_EIP - 2, vect); #endif INTERRUPT(vect, INTR_TYPE_SOFTINTR); return; } VERBOSE(("INT_Ib: VM86 && IOPL < 3 && INTn")); EXCEPTION(GP_EXCEPTION, 0); }
UINT8 ia32(void) { int rv; rv = sigsetjmp(exec_1step_jmpbuf, 1); switch (rv) { case 0: break; case 1: VERBOSE(("ia32: return from exception")); break; case 2: VERBOSE(("ia32: return from panic")); return FALSE; default: VERBOSE(("ia32: return from unknown cause")); break; } do { exec_1step(); if (CPU_TRAP) { CPU_DR6 |= CPU_DR6_BS; INTERRUPT(1, INTR_TYPE_EXCEPTION); dmax86(); } else if (dmac.working) { dmax86(); } if(np2break_is_next()) { return FALSE; } } while (CPU_REMCLOCK > 0 && !np2stopemulate); return TRUE; }