#define WEAK_PULLDN (PAD_CTL_PUS_100K_DOWN | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_HYS | PAD_CTL_SRE_SLOW) #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_HYS | PAD_CTL_SRE_SLOW) /* * */ static iomux_v3_cfg_t const init_pads[] = { /* bt_rfkill */ #define GP_BT_RFKILL_RESET IMX_GPIO_NR(6, 16) IOMUX_PAD_CTRL(NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM), /* ECSPI1 */ IOMUX_PAD_CTRL(EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL), IOMUX_PAD_CTRL(EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL), IOMUX_PAD_CTRL(EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL), #define GP_ECSPI1_NOR_CS IMX_GPIO_NR(3, 19) IOMUX_PAD_CTRL(EIM_D19__GPIO3_IO19, WEAK_PULLUP), /* ENET pads that don't change for PHY reset */ IOMUX_PAD_CTRL(ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL), IOMUX_PAD_CTRL(ENET_MDC__ENET_MDC, ENET_PAD_CTRL), IOMUX_PAD_CTRL(RGMII_TXC__RGMII_TXC, ENET_PAD_CTRL), IOMUX_PAD_CTRL(RGMII_TD0__RGMII_TD0, ENET_PAD_CTRL), IOMUX_PAD_CTRL(RGMII_TD1__RGMII_TD1, ENET_PAD_CTRL), IOMUX_PAD_CTRL(RGMII_TD2__RGMII_TD2, ENET_PAD_CTRL),
PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_SRE_SLOW) #define WEAK_PULLDOWN (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_SRE_SLOW) #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) /* * */ static const iomux_v3_cfg_t init_pads[] = { /* ECSPI1 pads */ IOMUX_PAD_CTRL(EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL), IOMUX_PAD_CTRL(EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL), IOMUX_PAD_CTRL(EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL), #define GP_ECSPI1_NOR_CS IMX_GPIO_NR(3, 19) IOMUX_PAD_CTRL(EIM_D19__GPIO3_IO19, SPI_PAD_CTRL), /* ENET pads that don't change for PHY reset */ IOMUX_PAD_CTRL(ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL), IOMUX_PAD_CTRL(ENET_MDC__ENET_MDC, ENET_PAD_CTRL), IOMUX_PAD_CTRL(RGMII_TXC__RGMII_TXC, ENET_PAD_CTRL), IOMUX_PAD_CTRL(RGMII_TD0__RGMII_TD0, ENET_PAD_CTRL), IOMUX_PAD_CTRL(RGMII_TD1__RGMII_TD1, ENET_PAD_CTRL), IOMUX_PAD_CTRL(RGMII_TD2__RGMII_TD2, ENET_PAD_CTRL), IOMUX_PAD_CTRL(RGMII_TD3__RGMII_TD3, ENET_PAD_CTRL), IOMUX_PAD_CTRL(RGMII_TX_CTL__RGMII_TX_CTL, ENET_PAD_CTRL), IOMUX_PAD_CTRL(ENET_REF_CLK__ENET_TX_CLK, ENET_PAD_CTRL),
#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_HYS | PAD_CTL_SRE_SLOW) #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) #define OUTPUT_40OHM_UP (OUTPUT_40OHM | PAD_CTL_PUS_100K_UP) #define OUTPUT_40OHM_DN (OUTPUT_40OHM | PAD_CTL_PUS_100K_DOWN) #define SPDIF_PAD_CTRL WEAK_PULLUP /* * */ static const iomux_v3_cfg_t init_pads[] = { /* Audio - GS2971, WM5102 */ IOMUX_PAD_CTRL(DISP0_DAT23__AUD4_RXD, AUD_PAD_CTRL), /* pin J3 - AOUT1/2 */ IOMUX_PAD_CTRL(SD2_CMD__AUD4_RXC, AUD_PAD_CTRL), /* pin J4 - ACLK*/ IOMUX_PAD_CTRL(DISP0_DAT18__AUD4_RXFS, AUD_PAD_CTRL), /* pin H4 - WCLK*/ /* Audio - TC3587 mipi hdmi input */ IOMUX_PAD_CTRL(DISP0_DAT13__AUD5_RXFS, AUD_PAD_CTRL), IOMUX_PAD_CTRL(DISP0_DAT14__AUD5_RXC, AUD_PAD_CTRL), IOMUX_PAD_CTRL(DISP0_DAT19__AUD5_RXD, AUD_PAD_CTRL), /* Audio - WM5102 */ IOMUX_PAD_CTRL(DI0_PIN2__AUD6_TXD, AUD_PAD_CTRL), IOMUX_PAD_CTRL(DI0_PIN3__AUD6_TXFS, AUD_PAD_CTRL), IOMUX_PAD_CTRL(DI0_PIN4__AUD6_RXD, AUD_PAD_CTRL), IOMUX_PAD_CTRL(DI0_PIN15__AUD6_TXC, AUD_PAD_CTRL), /* WM5102 */
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ PAD_CTL_HYS | PAD_CTL_SRE_FAST) #define WEAK_PULLDN (PAD_CTL_PUS_100K_DOWN | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_HYS | PAD_CTL_SRE_SLOW) #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_HYS | PAD_CTL_SRE_SLOW) static const iomux_v3_cfg_t init_pads[] = { /* bt_rfkill */ #define GP_BT_RFKILL_RESET IMX_GPIO_NR(6, 16) IOMUX_PAD_CTRL(NANDF_CS3__GPIO6_IO16, WEAK_PULLDN), /* ECSPI1 pads */ IOMUX_PAD_CTRL(EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL), IOMUX_PAD_CTRL(EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL), IOMUX_PAD_CTRL(EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL), #define GP_ECSPI1_NOR_CS IMX_GPIO_NR(3, 19) IOMUX_PAD_CTRL(EIM_D19__GPIO3_IO19, WEAK_PULLUP), /* i2c1 rtc rv4162 */ #define GPIRQ_RTC_RV4162 IMX_GPIO_NR(4, 9) IOMUX_PAD_CTRL(KEY_ROW1__GPIO4_IO09, WEAK_PULLUP), /* PCIe */ #define GP_PCIE_RESET IMX_GPIO_NR(2, 18) IOMUX_PAD_CTRL(EIM_A20__GPIO2_IO18, OUTPUT_40OHM),
PAD_CTL_SRE_FAST | PAD_CTL_HYS) #define WEAK_PULLDN (PAD_CTL_PUS_100K_DOWN | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_HYS | PAD_CTL_SRE_SLOW) #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_HYS | PAD_CTL_SRE_SLOW) /* * */ static const iomux_v3_cfg_t init_pads[] = { /* ECSPI1 */ IOMUX_PAD_CTRL(EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL), IOMUX_PAD_CTRL(EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL), IOMUX_PAD_CTRL(EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL), #define GP_ECSPI1_NOR_CS IMX_GPIO_NR(3, 19) IOMUX_PAD_CTRL(EIM_D19__GPIO3_IO19, WEAK_PULLUP), /* SS1 */ /* ECSPI3 - GS2971 */ IOMUX_PAD_CTRL(DISP0_DAT2__ECSPI3_MISO, SPI_PAD_CTRL), /* pin E7 - SDOUT */ IOMUX_PAD_CTRL(DISP0_DAT1__ECSPI3_MOSI, SPI_PAD_CTRL), /* pin E8 - SDIN */ IOMUX_PAD_CTRL(DISP0_DAT0__ECSPI3_SCLK, SPI_PAD_CTRL), /* pin F8 - SCLK */ #define GP_ECSPI3_GS2971_CS IMX_GPIO_NR(4, 24) IOMUX_PAD_CTRL(DISP0_DAT3__GPIO4_IO24, WEAK_PULLUP), /* 0 - pin F7 - CS0 */ /* ENET pads that don't change for PHY reset */ IOMUX_PAD_CTRL(ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL), IOMUX_PAD_CTRL(ENET_MDC__ENET_MDC, ENET_PAD_CTRL),
PAD_CTL_SRE_FAST | PAD_CTL_HYS) #define WEAK_PULLDN (PAD_CTL_PUS_100K_DOWN | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_HYS | PAD_CTL_SRE_SLOW) #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_HYS | PAD_CTL_SRE_SLOW) /* * */ static iomux_v3_cfg_t const init_pads[] = { /* ECSPI1 */ IOMUX_PAD_CTRL(EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL), IOMUX_PAD_CTRL(EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL), IOMUX_PAD_CTRL(EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL), #define GP_ECSPI1_NOR_CS IMX_GPIO_NR(3, 19) IOMUX_PAD_CTRL(EIM_D19__GPIO3_IO19, WEAK_PULLUP), /* ENET pads that don't change for PHY reset */ IOMUX_PAD_CTRL(ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL), IOMUX_PAD_CTRL(ENET_MDC__ENET_MDC, ENET_PAD_CTRL), IOMUX_PAD_CTRL(RGMII_TXC__RGMII_TXC, ENET_PAD_CTRL), IOMUX_PAD_CTRL(RGMII_TD0__RGMII_TD0, ENET_PAD_CTRL), IOMUX_PAD_CTRL(RGMII_TD1__RGMII_TD1, ENET_PAD_CTRL), IOMUX_PAD_CTRL(RGMII_TD2__RGMII_TD2, ENET_PAD_CTRL), IOMUX_PAD_CTRL(RGMII_TD3__RGMII_TD3, ENET_PAD_CTRL), IOMUX_PAD_CTRL(RGMII_TX_CTL__RGMII_TX_CTL, ENET_PAD_CTRL), IOMUX_PAD_CTRL(ENET_REF_CLK__ENET_TX_CLK, ENET_PAD_CTRL),
PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_SRE_SLOW) #define WEAK_PULLUP (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_SRE_SLOW) /* * */ static const iomux_v3_cfg_t init_pads[] = { /* bt_rfkill */ #define GP_BRM_BT_RESET IMX_GPIO_NR(6, 8) IOMUX_PAD_CTRL(NANDF_ALE__GPIO6_IO08, WEAK_PULLDN), #define GP_BRM_BT_SHUTDOWN IMX_GPIO_NR(6, 15) IOMUX_PAD_CTRL(NANDF_CS2__GPIO6_IO15, WEAK_PULLDN), IOMUX_PAD_CTRL(NANDF_CS3__GPIO6_IO16, WEAK_PULLUP), /* ECSPI1 */ IOMUX_PAD_CTRL(EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL), IOMUX_PAD_CTRL(EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL), IOMUX_PAD_CTRL(EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL), #define GP_ECSPI1_NOR_CS IMX_GPIO_NR(3, 19) IOMUX_PAD_CTRL(EIM_D19__GPIO3_IO19, SPI_PAD_CTRL), /* ENET pads that don't change for PHY reset */ IOMUX_PAD_CTRL(ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL), IOMUX_PAD_CTRL(ENET_MDC__ENET_MDC, ENET_PAD_CTRL), IOMUX_PAD_CTRL(RGMII_TXC__RGMII_TXC, ENET_PAD_CTRL),
#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_HYS | PAD_CTL_SRE_SLOW) #define WEAK_PULLUP_OUTPUT (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_SRE_SLOW) /* * */ static const iomux_v3_cfg_t init_pads[] = { /* HOG */ #define GP_MAIN_POWER_EN IMX_GPIO_NR(3, 5) IOMUX_PAD_CTRL(EIM_DA5__GPIO3_IO05, WEAK_PULLDN_OUTPUT), #define GP_MAIN_POWER_BUTTON IMX_GPIO_NR(3, 6) IOMUX_PAD_CTRL(EIM_DA6__GPIO3_IO06, WEAK_PULLUP), /* ADV7180 */ /* camera - video0 - ADV7180 - I2C3, crystal 28.636 MHz */ IOMUX_PAD_CTRL(CSI0_DAT12__IPU1_CSI0_DATA12, CSI_PAD_CTRL), IOMUX_PAD_CTRL(CSI0_DAT13__IPU1_CSI0_DATA13, CSI_PAD_CTRL), IOMUX_PAD_CTRL(CSI0_DAT14__IPU1_CSI0_DATA14, CSI_PAD_CTRL), IOMUX_PAD_CTRL(CSI0_DAT15__IPU1_CSI0_DATA15, CSI_PAD_CTRL), IOMUX_PAD_CTRL(CSI0_DAT16__IPU1_CSI0_DATA16, CSI_PAD_CTRL), IOMUX_PAD_CTRL(CSI0_DAT17__IPU1_CSI0_DATA17, CSI_PAD_CTRL), IOMUX_PAD_CTRL(CSI0_DAT18__IPU1_CSI0_DATA18, CSI_PAD_CTRL), IOMUX_PAD_CTRL(CSI0_DAT19__IPU1_CSI0_DATA19, CSI_PAD_CTRL), IOMUX_PAD_CTRL(CSI0_PIXCLK__IPU1_CSI0_PIXCLK, CSI_PAD_CTRL), IOMUX_PAD_CTRL(CSI0_MCLK__GPIO5_IO19, WEAK_PULLUP), /* Hsync */
PAD_CTL_HYS | PAD_CTL_SRE_FAST) #define WEAK_PULLDN (PAD_CTL_PUS_100K_DOWN | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_HYS | PAD_CTL_SRE_SLOW) #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_HYS | PAD_CTL_SRE_SLOW) /* * */ static const iomux_v3_cfg_t init_pads[] = { /* ECSPI1 */ IOMUX_PAD_CTRL(EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL), IOMUX_PAD_CTRL(EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL), IOMUX_PAD_CTRL(EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL), #define GP_ECSPI1_NOR_CS IMX_GPIO_NR(3, 19) IOMUX_PAD_CTRL(EIM_D19__GPIO3_IO19, WEAK_PULLUP), /* ENET pads that don't change for PHY reset */ IOMUX_PAD_CTRL(ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL), IOMUX_PAD_CTRL(ENET_MDC__ENET_MDC, ENET_PAD_CTRL), IOMUX_PAD_CTRL(RGMII_TXC__RGMII_TXC, ENET_PAD_CTRL), IOMUX_PAD_CTRL(RGMII_TD0__RGMII_TD0, ENET_PAD_CTRL), IOMUX_PAD_CTRL(RGMII_TD1__RGMII_TD1, ENET_PAD_CTRL), IOMUX_PAD_CTRL(RGMII_TD2__RGMII_TD2, ENET_PAD_CTRL), IOMUX_PAD_CTRL(RGMII_TD3__RGMII_TD3, ENET_PAD_CTRL), IOMUX_PAD_CTRL(RGMII_TX_CTL__RGMII_TX_CTL, ENET_PAD_CTRL), IOMUX_PAD_CTRL(ENET_REF_CLK__ENET_TX_CLK, ENET_PAD_CTRL),
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_SRE_SLOW) #define WEAK_PULLDN (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_SRE_SLOW) /* * */ static iomux_v3_cfg_t const init_pads[] = { /* bt_rfkill */ #define GP_BT_RFKILL_RESET IMX_GPIO_NR(6, 16) IOMUX_PAD_CTRL(NANDF_CS3__GPIO6_IO16, WEAK_PULLDN), /* ECSPI1 */ IOMUX_PAD_CTRL(EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL), IOMUX_PAD_CTRL(EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL), IOMUX_PAD_CTRL(EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL), #define GP_ECSPI1_NOR_CS IMX_GPIO_NR(3, 19) IOMUX_PAD_CTRL(EIM_D19__GPIO3_IO19, SPI_PAD_CTRL), /* gpio_Keys */ #define GP_GPIOKEY_BACK IMX_GPIO_NR(7, 13) IOMUX_PAD_CTRL(GPIO_18__GPIO7_IO13, WEAK_PULLUP), #define GP_GPIOKEY_HOME IMX_GPIO_NR(4, 5) IOMUX_PAD_CTRL(GPIO_19__GPIO4_IO05, WEAK_PULLUP), /* gpios */