s8 dce_mode_program(s32 output_name)
{
struct output *o=®istry[output_name].output;
void *sysname=(void*)udev_device_get_sysname(o->d);
//----------------------------------------------------------------------------
//alloc a properly sized double buffered frame buffer
o->fb.align=PAGE_SZ;//align on a cpu memory page
u64 sz=2*(o->current->h*o->current->v*alga_pixel_fmts_sz[o->pixel_fmt]);
o->fb.sz=sz;
ul req=IOWR('d',SI_MEM_ALLOC,o->fb);
l r=ioctl(o->fd,req,(l)&o->fb);
if(ISERR(r)){
PERR("output:%s:dce:unable to allocate proper vram for a frame buffer of"
" size %llu bytes\n",sysname,o->fb.sz);
goto err;
}
LOG("output:%s:dce:double buffered frame buffer of %llu bytes allocated\n",
sysname,sz);
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
//program synchronously the video mode
struct si_dce_dp_set dp_set;
dp_set.idx=o->blk_idx;
dp_set.primary=o->fb.gpu_addr;
dp_set.secondary=o->fb.gpu_addr+sz/2;
dp_set.pixel_fmt=o->pixel_fmt;
dp_set.timing=*(o->current);
dp_set.pitch=o->current->h;
req=IOW('d',SI_DCE_DP_SET,dp_set);
r=ioctl(o->fd,req,(l)&dp_set);
if(ISERR(r)){
PERR("output:%s:dce:%ux%u@%u: unable to program\n",sysname,o->current->h,
o->current->v,v_refresh(o->current));
goto err_free_fb;
}
//----------------------------------------------------------------------------
LOG("output:%s:dce:%ux%u@%u:programmed successfully\n",sysname,o->current->h,
o->current->v,v_refresh(o->current));
return LWL_OK;
err_free_fb:
req=IOW('d',SI_MEM_FREE,o->fb.gpu_addr);
r=ioctl(o->fd,req,&o->fb.gpu_addr);
if(ISERR(r))
PERR("output:%s:dce:unable to free frame buffer memory (LEAK!)\n",sysname);
err:
return LWL_ERR;
}
void
smdk2800_io_init(void)
{
unsigned int hclk;
unsigned int pclk;
unsigned int tmdat;
#define O PCON_OUTPUT
#define I PCON_INPUT
#define A PCON_ALTFUN
#define _ 0
#define _C(b7,b6,b5,b4,b3,b2,b1,b0) \
((b7<<14)|(b6<<12)|(b5<<10)|(b4<<8)|(b3<<6)|(b2<<4)|(b1<<2)|(b0<<0))
/* GPIO port */
IOW(S3C2800_GPIO_BASE+GPIO_PCONA, _C(O,O,A,A,A,A,A,A));
IOW(S3C2800_GPIO_BASE+GPIO_PUPA, 0xff);
IOW(S3C2800_GPIO_BASE+GPIO_PCONB, _C(I,O,A,A,A,A,A,A));
IOW(S3C2800_GPIO_BASE+GPIO_PCONC, _C(_,_,_,_,O,A,A,A));
IOW(S3C2800_GPIO_BASE+GPIO_PUPC, 0xff);
IOW(S3C2800_GPIO_BASE+GPIO_PCOND, _C(A,A,A,A,A,A,A,A));
IOW(S3C2800_GPIO_BASE+GPIO_PUPD, 0xff);
IOW(S3C2800_GPIO_BASE+GPIO_PCONE, _C(O,O,O,O,A,A,A,A));
IOW(S3C2800_GPIO_BASE+GPIO_PUPE, 0xff);
IOW(S3C2800_GPIO_BASE+GPIO_PCONF, _C(A,A,A,A,A,A,A,A));
IOW(S3C2800_GPIO_BASE+GPIO_PUPF, 0xff);
IOW(S3C2800_GPIO_BASE+GPIO_EXTINTR, EXTINTR_INIT);
#undef O
#undef I
#undef A
#undef _
#undef _C
/* Get clock value */
if(IOR(S3C2800_CLKMAN_BASE+CLKMAN_CLKCON) & CLKCON_HCLK)
hclk = FCLK / 2;
else
hclk = FCLK;
if(IOR(S3C2800_CLKMAN_BASE+CLKMAN_CLKCON) & CLKCON_PCLK)
pclk = hclk / 2;
else
pclk = hclk;
/* Timer */
if((pclk/F_1MHZ) < 1)
tmdat = 1<<16;
else
tmdat = (pclk/F_1MHZ)<<16;
#define TMDAT_INIT 0xf424
IOW(S3C2800_TIMER0_BASE+TIMER_TMDAT, (tmdat | TMDAT_INIT));
IOW(S3C2800_TIMER1_BASE+TIMER_TMDAT, (tmdat | TMDAT_INIT));
IOW(S3C2800_TIMER2_BASE+TIMER_TMDAT, (tmdat | TMDAT_INIT));
IOW(S3C2800_TIMER0_BASE+TIMER_TMCON, TMCON_MUX_DIV32 | TMCON_INTENA | TMCON_ENABLE);
IOW(S3C2800_TIMER1_BASE+TIMER_TMCON, TMCON_MUX_DIV16 | TMCON_INTENA | TMCON_ENABLE);
IOW(S3C2800_TIMER2_BASE+TIMER_TMCON, TMCON_MUX_DIV8 | TMCON_INTENA | TMCON_ENABLE);
/* Interrupt controller */
IOW(S3C2800_INTCTL_BASE+INTCTL_INTMOD, 0);
IOW(S3C2800_INTCTL_BASE+INTCTL_INTMSK, 0);
/* Initial complete */
SETLED(0x0); /* All LEDs on (o o o) */
}
