static void
isic_enable_intr(struct isic_softc *sc, int enable)
{
#if NNISACSX > 0
if (sc->sc_cardtyp == CARD_TYPEP_AVMA1PCIV2) {
if (enable)
isic_isacsx_init(sc);
else isic_isacsx_disable_intr(sc);
return;
}
#endif /* NNISACSX > 0 */
#if NNISAC > 0
if (enable) {
isic_isac_init(sc);
} else {
/* disable receiver */
ISAC_WRITE(I_MODE, ISAC_MODE_MDS2|ISAC_MODE_MDS1|ISAC_MODE_DIM0);
/* mask interrupts */
if (sc->sc_ipac) {
IPAC_WRITE(IPAC_MASK, 0xff);
} else {
ISAC_WRITE(I_MASK, 0xff);
}
}
#endif /* NNISAC > 0 */
}
/*---------------------------------------------------------------------------*
* L1 ISACSX disable interrupts
*---------------------------------------------------------------------------*/
void
isic_isacsx_disable_intr(struct isic_softc *sc)
{
ISAC_WRITE(I_WMODED, ISACSX_MODED_MDS2|ISACSX_MODED_MDS1|ISACSX_MODED_DIM0);
isacsx_imaskd = 0xff; /* disable all irqs */
isacsx_imask = 0xff; /* disable all irqs */
ISAC_WRITE(I_MASKD, isacsx_imaskd);
ISAC_WRITE(I_MASK, isacsx_imask);
}
/*---------------------------------------------------------------------------*
* isic_recovery - try to recover from irq lockup
*---------------------------------------------------------------------------*/
void
isic_recover(struct isic_softc *sc)
{
u_char byte;
/* get hscx irq status from hscx b ista */
byte = HSCX_READ(HSCX_CH_B, H_ISTA);
NDBGL1(L1_ERROR, "HSCX B: ISTA = 0x%x", byte);
if(byte & HSCX_ISTA_ICA)
NDBGL1(L1_ERROR, "HSCX A: ISTA = 0x%x", (u_char)HSCX_READ(HSCX_CH_A, H_ISTA));
if(byte & HSCX_ISTA_EXB)
NDBGL1(L1_ERROR, "HSCX B: EXIR = 0x%x", (u_char)HSCX_READ(HSCX_CH_B, H_EXIR));
if(byte & HSCX_ISTA_EXA)
NDBGL1(L1_ERROR, "HSCX A: EXIR = 0x%x", (u_char)HSCX_READ(HSCX_CH_A, H_EXIR));
/* get isac irq status */
byte = ISAC_READ(I_ISTA);
NDBGL1(L1_ERROR, " ISAC: ISTA = 0x%x", byte);
if(byte & ISAC_ISTA_EXI)
NDBGL1(L1_ERROR, " ISAC: EXIR = 0x%x", (u_char)ISAC_READ(I_EXIR));
if(byte & ISAC_ISTA_CISQ)
{
byte = ISAC_READ(I_CIRR);
NDBGL1(L1_ERROR, " ISAC: CISQ = 0x%x", byte);
if(byte & ISAC_CIRR_SQC)
NDBGL1(L1_ERROR, " ISAC: SQRR = 0x%x", (u_char)ISAC_READ(I_SQRR));
}
NDBGL1(L1_ERROR, "HSCX B: IMASK = 0x%x", HSCX_B_IMASK);
NDBGL1(L1_ERROR, "HSCX A: IMASK = 0x%x", HSCX_A_IMASK);
HSCX_WRITE(0, H_MASK, 0xff);
HSCX_WRITE(1, H_MASK, 0xff);
DELAY(100);
HSCX_WRITE(0, H_MASK, HSCX_A_IMASK);
HSCX_WRITE(1, H_MASK, HSCX_B_IMASK);
DELAY(100);
NDBGL1(L1_ERROR, " ISAC: IMASK = 0x%x", ISAC_IMASK);
ISAC_WRITE(I_MASK, 0xff);
DELAY(100);
ISAC_WRITE(I_MASK, ISAC_IMASK);
}
/*---------------------------------------------------------------------------*
* L1 ISACSX initialization
*---------------------------------------------------------------------------*/
int
isic_isacsx_init(struct isic_softc *sc)
{
isacsx_imaskd = 0xff; /* disable all irqs */
isacsx_imask = 0xff; /* disable all irqs */
ISAC_WRITE(I_MASKD, isacsx_imaskd);
ISAC_WRITE(I_MASK, isacsx_imask);
/* the ISACSX only runs in IOM-2 mode */
NDBGL1(L1_I_SETUP, "configuring for IOM-2 mode");
/* TR_CONF0: Transceiver Configuration Register 0:
* DIS_TR - transceiver enabled
* EN_ICV - normal operation
* EXLP - no external loop
* LDD - automatic clock generation
*/
ISAC_WRITE(I_WTR_CONF0, 0);
/* TR_CONF2: Transceiver Configuration Register 1:
* DIS_TX - transmitter enabled
* PDS - phase deviation 2 S-bits
* RLP - remote line loop open
*/
ISAC_WRITE(I_WTR_CONF2, 0);
/* MODED: Mode Register:
* MDSx - transparent mode 0
* TMD - timer mode = external
* RAC - Receiver enabled
* DIMx - digital i/f mode
*/
ISAC_WRITE(I_WMODED, ISACSX_MODED_MDS2|ISACSX_MODED_MDS1|ISACSX_MODED_RAC|ISACSX_MODED_DIM0);
/* enabled interrupts:
* ===================
* RME - receive message end
* RPF - receive pool full
* RPO - receive pool overflow
* XPR - transmit pool ready
* XMR - transmit message repeat
* XDU - transmit data underrun
*/
isacsx_imaskd = ISACSX_MASKD_LOW;
ISAC_WRITE(I_MASKD, isacsx_imaskd);
/* enabled interrupts:
* ===================
* ICD - HDLC interrupt from D-channel
* CIC - C/I channel change
*/
isacsx_imask = ~(ISACSX_MASK_ICD | ISACSX_MASK_CIC);
ISAC_WRITE(I_MASK, isacsx_imask);
return(0);
}
void
avm_pnp_intr(int unit)
{
struct isic_softc *sc;
u_char stat;
register u_char isac_irq_stat;
int was_isac = 0;
sc = &isic_sc[unit];
for(;;) {
stat = inb(sc->sc_port + STAT0_OFFSET);
DBGL1(L1_H_IRQ, "avm_pnp_intr", ("stat %x\n", stat));
/* was there an interrupt from this card ? */
if ((stat & ASL_IRQ_Pending) == ASL_IRQ_Pending)
break; /* no */
/* interrupts are low active */
if (!(stat & ASL_IRQ_TIMER))
DBGL1(L1_H_IRQ, "avm_pnp_intr", ("timer interrupt ???\n"));
if (!(stat & ASL_IRQ_ISAC))
{
DBGL1(L1_H_IRQ, "avm_pnp_intr", ("ISAC\n"));
isac_irq_stat = ISAC_READ(I_ISTA);
isic_isac_irq(sc, isac_irq_stat);
was_isac = 1;
}
if (!(stat & ASL_IRQ_HSCX))
{
DBGL1(L1_H_IRQ, "avm_pnp_intr", ("HSCX\n"));
avm_pnp_hscx_int_handler(sc);
}
}
if (was_isac) {
ISAC_WRITE(0x20, 0xFF);
ISAC_WRITE(0x20, 0x0);
}
}
/*---------------------------------------------------------------------------*
* ISACSX recover - try to recover from irq lockup
*---------------------------------------------------------------------------*/
void
isic_isacsx_recover(struct isic_softc *sc)
{
u_char byte, istad;
/*
* XXX
* Leo: Unknown if this function does anything good... At least it
* prints some stuff that might be helpful.
*/
printf("%s: isic_isacsx_recover\n", device_xname(&sc->sc_dev));
/* get isac irq status */
byte = ISAC_READ(I_ISTAD);
NDBGL1(L1_ERROR, " ISAC: ISTAD = 0x%x", byte);
if(byte & ISACSX_ISTA_ICD) {
istad = ISAC_READ(I_ISTAD);
NDBGL1(L1_ERROR, " ISACSX: istad = 0x%02x", istad);
}
if(byte & ISACSX_ISTA_CIC)
{
byte = ISAC_READ(I_CIR0);
NDBGL1(L1_ERROR, " ISACSX: CIR0 = 0x%x", byte);
}
NDBGL1(L1_ERROR, " ISACSX: IMASKD/IMASK = 0x%02x/%02x", isacsx_imaskd,
isacsx_imask);
ISAC_WRITE(I_MASKD, 0xff);
ISAC_WRITE(I_MASK, 0xff);
DELAY(100);
ISAC_WRITE(I_MASKD, isacsx_imaskd);
ISAC_WRITE(I_MASK, isacsx_imask);
}
/*---------------------------------------------------------------------------*
* execute a layer 1 command
*---------------------------------------------------------------------------*/
void
isic_isacsx_l1_cmd(struct isic_softc *sc, int command)
{
u_char cmd;
#ifdef I4B_SMP_WORKAROUND
/* XXXXXXXXXXXXXXXXXXX */
/*
* patch from Wolfgang Helbig:
*
* Here is a patch that makes i4b work on an SMP:
* The card (TELES 16.3) didn't interrupt on an SMP machine.
* This is a gross workaround, but anyway it works *and* provides
* some information as how to finally fix this problem.
*/
HSCX_WRITE(0, H_MASK, 0xff);
HSCX_WRITE(1, H_MASK, 0xff);
ISAC_WRITE(I_MASKD, 0xff);
ISAC_WRITE(I_MASK, 0xff);
DELAY(100);
HSCX_WRITE(0, H_MASK, HSCX_A_IMASK);
HSCX_WRITE(1, H_MASK, HSCX_B_IMASK);
ISAC_WRITE(I_MASKD, isacsx_imaskd);
ISAC_WRITE(I_MASK, isacsx_imask);
/* XXXXXXXXXXXXXXXXXXX */
#endif /* I4B_SMP_WORKAROUND */
if(command < 0 || command > CMD_ILL)
{
NDBGL1(L1_I_ERR, "illegal cmd 0x%x in state %s", command, isic_printstate(sc));
return;
}
cmd = ISACSX_CIX0_LOW;
switch(command)
{
case CMD_TIM:
NDBGL1(L1_I_CICO, "tx TIM in state %s", isic_printstate(sc));
cmd |= (ISACSX_CIX0_CTIM << 4);
break;
case CMD_RS:
NDBGL1(L1_I_CICO, "tx RS in state %s", isic_printstate(sc));
cmd |= (ISACSX_CIX0_CRS << 4);
break;
case CMD_AR8:
NDBGL1(L1_I_CICO, "tx AR8 in state %s", isic_printstate(sc));
cmd |= (ISACSX_CIX0_CAR8 << 4);
break;
case CMD_AR10:
NDBGL1(L1_I_CICO, "tx AR10 in state %s", isic_printstate(sc));
cmd |= (ISACSX_CIX0_CAR10 << 4);
break;
case CMD_DIU:
NDBGL1(L1_I_CICO, "tx DIU in state %s", isic_printstate(sc));
cmd |= (ISACSX_CIX0_CDIU << 4);
break;
}
ISAC_WRITE(I_CIX0, cmd);
}
/*---------------------------------------------------------------------------*
*
* L2 -> L1: PH-DATA-REQUEST
* =========================
*
* parms:
* unit physical interface unit number
* m mbuf containing L2 frame to be sent out
* freeflag MBUF_FREE: free mbuf here after having sent
* it out
* MBUF_DONTFREE: mbuf is freed by Layer 2
* returns:
* ==0 fail, nothing sent out
* !=0 ok, frame sent out
*
*---------------------------------------------------------------------------*/
int
ifpi_ph_data_req(int unit, struct mbuf *m, int freeflag)
{
u_char cmd;
struct l1_softc *sc = ifpi_scp[unit];
#ifdef NOTDEF
NDBGL1(L1_PRIM, "PH-DATA-REQ, unit %d, freeflag=%d", unit, freeflag);
#endif
if(m == NULL) /* failsafe */
return (0);
crit_enter();
if(sc->sc_I430state == ST_F3) /* layer 1 not running ? */
{
NDBGL1(L1_I_ERR, "still in state F3!");
ifpi_ph_activate_req(unit);
}
if(sc->sc_state & ISAC_TX_ACTIVE)
{
if(sc->sc_obuf2 == NULL)
{
sc->sc_obuf2 = m; /* save mbuf ptr */
if(freeflag)
sc->sc_freeflag2 = 1; /* IRQ must mfree */
else
sc->sc_freeflag2 = 0; /* IRQ must not mfree */
NDBGL1(L1_I_MSG, "using 2nd ISAC TX buffer, state = %s", ifpi_printstate(sc));
if(sc->sc_trace & TRACE_D_TX)
{
i4b_trace_hdr_t hdr;
hdr.unit = L0IFPIUNIT(unit);
hdr.type = TRC_CH_D;
hdr.dir = FROM_TE;
hdr.count = ++sc->sc_trace_dcount;
MICROTIME(hdr.time);
i4b_l1_trace_ind(&hdr, m->m_len, m->m_data);
}
crit_exit();
return(1);
}
NDBGL1(L1_I_ERR, "No Space in TX FIFO, state = %s", ifpi_printstate(sc));
if(freeflag == MBUF_FREE)
i4b_Dfreembuf(m);
crit_exit();
return (0);
}
if(sc->sc_trace & TRACE_D_TX)
{
i4b_trace_hdr_t hdr;
hdr.unit = L0IFPIUNIT(unit);
hdr.type = TRC_CH_D;
hdr.dir = FROM_TE;
hdr.count = ++sc->sc_trace_dcount;
MICROTIME(hdr.time);
i4b_l1_trace_ind(&hdr, m->m_len, m->m_data);
}
sc->sc_state |= ISAC_TX_ACTIVE; /* set transmitter busy flag */
NDBGL1(L1_I_MSG, "ISAC_TX_ACTIVE set");
sc->sc_freeflag = 0; /* IRQ must NOT mfree */
ISAC_WRFIFO(m->m_data, min(m->m_len, ISAC_FIFO_LEN)); /* output to TX fifo */
if(m->m_len > ISAC_FIFO_LEN) /* message > 32 bytes ? */
{
sc->sc_obuf = m; /* save mbuf ptr */
sc->sc_op = m->m_data + ISAC_FIFO_LEN; /* ptr for irq hdl */
sc->sc_ol = m->m_len - ISAC_FIFO_LEN; /* length for irq hdl */
if(freeflag)
sc->sc_freeflag = 1; /* IRQ must mfree */
cmd = ISAC_CMDR_XTF;
}
else
{
sc->sc_obuf = NULL;
sc->sc_op = NULL;
sc->sc_ol = 0;
if(freeflag)
i4b_Dfreembuf(m);
cmd = ISAC_CMDR_XTF | ISAC_CMDR_XME;
}
ISAC_WRITE(I_CMDR, cmd);
ISACCMDRWRDELAY();
crit_exit();
return(1);
}
/*---------------------------------------------------------------------------*
* ISAC interrupt service routine
*---------------------------------------------------------------------------*/
void
isic_isac_irq(struct isic_softc *sc, int ista)
{
register u_char c = 0;
NDBGL1(L1_F_MSG, "%s: ista = 0x%02x", device_xname(&sc->sc_dev), ista);
if(ista & ISAC_ISTA_EXI) /* extended interrupt */
{
u_int8_t exirstat = ISAC_READ(I_EXIR);
if (sc->sc_intr_valid == ISIC_INTR_VALID)
c |= isic_isac_exir_hdlr(sc, exirstat);
}
if(ista & ISAC_ISTA_RME) /* receive message end */
{
register int rest;
u_char rsta;
/* get rx status register */
rsta = ISAC_READ(I_RSTA);
if((rsta & ISAC_RSTA_MASK) != 0x20)
{
int error = 0;
if(!(rsta & ISAC_RSTA_CRC)) /* CRC error */
{
error++;
NDBGL1(L1_I_ERR, "%s: CRC error", device_xname(&sc->sc_dev));
}
if(rsta & ISAC_RSTA_RDO) /* ReceiveDataOverflow */
{
error++;
NDBGL1(L1_I_ERR, "%s: Data Overrun error", device_xname(&sc->sc_dev));
}
if(rsta & ISAC_RSTA_RAB) /* ReceiveABorted */
{
error++;
NDBGL1(L1_I_ERR, "%s: Receive Aborted error", device_xname(&sc->sc_dev));
}
if(error == 0)
{
NDBGL1(L1_I_ERR, "%s: RME unknown error, RSTA = 0x%02x!", device_xname(&sc->sc_dev), rsta);
}
i4b_Dfreembuf(sc->sc_ibuf);
c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES;
sc->sc_ibuf = NULL;
sc->sc_ib = NULL;
sc->sc_ilen = 0;
ISAC_WRITE(I_CMDR, ISAC_CMDR_RMC|ISAC_CMDR_RRES);
ISACCMDRWRDELAY();
return;
}
rest = (ISAC_READ(I_RBCL) & (ISAC_FIFO_LEN-1));
if(rest == 0)
rest = ISAC_FIFO_LEN;
if(sc->sc_ibuf == NULL)
{
if((sc->sc_ibuf = i4b_Dgetmbuf(rest)) != NULL)
sc->sc_ib = sc->sc_ibuf->m_data;
else
panic("isic_isac_irq: RME, i4b_Dgetmbuf returns NULL!");
sc->sc_ilen = 0;
}
if(sc->sc_ilen <= (MAX_DFRAME_LEN - rest))
{
ISAC_RDFIFO(sc->sc_ib, rest);
sc->sc_ilen += rest;
sc->sc_ibuf->m_pkthdr.len =
sc->sc_ibuf->m_len = sc->sc_ilen;
if(sc->sc_trace & TRACE_D_RX)
{
i4b_trace_hdr hdr;
memset(&hdr, 0, sizeof hdr);
hdr.type = TRC_CH_D;
hdr.dir = FROM_NT;
hdr.count = ++sc->sc_trace_dcount;
isdn_layer2_trace_ind(&sc->sc_l2, sc->sc_l3token, &hdr, sc->sc_ibuf->m_len, sc->sc_ibuf->m_data);
}
c |= ISAC_CMDR_RMC;
if(sc->sc_intr_valid == ISIC_INTR_VALID &&
(((struct isdn_l3_driver*)sc->sc_l3token)->protocol != PROTOCOL_D64S))
{
isdn_layer2_data_ind(&sc->sc_l2, sc->sc_l3token, sc->sc_ibuf);
}
else
{
i4b_Dfreembuf(sc->sc_ibuf);
}
}
else
{
NDBGL1(L1_I_ERR, "RME, input buffer overflow!");
i4b_Dfreembuf(sc->sc_ibuf);
c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES;
}
sc->sc_ibuf = NULL;
sc->sc_ib = NULL;
sc->sc_ilen = 0;
}
if(ista & ISAC_ISTA_RPF) /* receive fifo full */
{
if(sc->sc_ibuf == NULL)
{
if((sc->sc_ibuf = i4b_Dgetmbuf(MAX_DFRAME_LEN)) != NULL)
sc->sc_ib= sc->sc_ibuf->m_data;
else
panic("isic_isac_irq: RPF, i4b_Dgetmbuf returns NULL!");
sc->sc_ilen = 0;
}
if(sc->sc_ilen <= (MAX_DFRAME_LEN - ISAC_FIFO_LEN))
{
ISAC_RDFIFO(sc->sc_ib, ISAC_FIFO_LEN);
sc->sc_ilen += ISAC_FIFO_LEN;
sc->sc_ib += ISAC_FIFO_LEN;
c |= ISAC_CMDR_RMC;
}
else
{
NDBGL1(L1_I_ERR, "RPF, input buffer overflow!");
i4b_Dfreembuf(sc->sc_ibuf);
sc->sc_ibuf = NULL;
sc->sc_ib = NULL;
sc->sc_ilen = 0;
c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES;
}
}
if(ista & ISAC_ISTA_XPR) /* transmit fifo empty (XPR bit set) */
{
if((sc->sc_obuf2 != NULL) && (sc->sc_obuf == NULL))
{
sc->sc_freeflag = sc->sc_freeflag2;
sc->sc_obuf = sc->sc_obuf2;
sc->sc_op = sc->sc_obuf->m_data;
sc->sc_ol = sc->sc_obuf->m_len;
sc->sc_obuf2 = NULL;
#ifdef NOTDEF
printf("ob2=%x, op=%x, ol=%d, f=%d #",
sc->sc_obuf,
sc->sc_op,
sc->sc_ol,
sc->sc_state);
#endif
}
else
{
#ifdef NOTDEF
printf("ob=%x, op=%x, ol=%d, f=%d #",
sc->sc_obuf,
sc->sc_op,
sc->sc_ol,
sc->sc_state);
#endif
}
if(sc->sc_obuf)
{
ISAC_WRFIFO(sc->sc_op, min(sc->sc_ol, ISAC_FIFO_LEN));
if(sc->sc_ol > ISAC_FIFO_LEN) /* length > 32 ? */
{
sc->sc_op += ISAC_FIFO_LEN; /* bufferptr+32 */
sc->sc_ol -= ISAC_FIFO_LEN; /* length - 32 */
c |= ISAC_CMDR_XTF; /* set XTF bit */
}
else
{
if(sc->sc_freeflag)
{
i4b_Dfreembuf(sc->sc_obuf);
sc->sc_freeflag = 0;
}
sc->sc_obuf = NULL;
sc->sc_op = NULL;
sc->sc_ol = 0;
c |= ISAC_CMDR_XTF | ISAC_CMDR_XME;
}
}
else
{
sc->sc_state &= ~ISAC_TX_ACTIVE;
}
}
if(ista & ISAC_ISTA_CISQ) /* channel status change CISQ */
{
register u_char ci;
/* get command/indication rx register*/
ci = ISAC_READ(I_CIRR);
/* if S/Q IRQ, read SQC reg to clr SQC IRQ */
if(ci & ISAC_CIRR_SQC)
(void) ISAC_READ(I_SQRR);
/* C/I code change IRQ (flag already cleared by CIRR read) */
if(ci & ISAC_CIRR_CIC0)
isic_isac_ind_hdlr(sc, (ci >> 2) & 0xf);
}
if(c)
{
ISAC_WRITE(I_CMDR, c);
ISACCMDRWRDELAY();
}
}
/*---------------------------------------------------------------------------*
* ISAC interrupt service routine
*---------------------------------------------------------------------------*/
void
ifpnp_isac_irq(struct l1_softc *sc, int ista)
{
u_char c = 0;
NDBGL1(L1_F_MSG, "unit %d: ista = 0x%02x", sc->sc_unit, ista);
if(ista & ISAC_ISTA_EXI) /* extended interrupt */
{
c |= ifpnp_isac_exir_hdlr(sc, ISAC_READ(I_EXIR));
}
if(ista & ISAC_ISTA_RME) /* receive message end */
{
int rest;
u_char rsta;
/* get rx status register */
rsta = ISAC_READ(I_RSTA);
if((rsta & ISAC_RSTA_MASK) != 0x20)
{
int error = 0;
if(!(rsta & ISAC_RSTA_CRC)) /* CRC error */
{
error++;
NDBGL1(L1_I_ERR, "unit %d: CRC error", sc->sc_unit);
}
if(rsta & ISAC_RSTA_RDO) /* ReceiveDataOverflow */
{
error++;
NDBGL1(L1_I_ERR, "unit %d: Data Overrun error", sc->sc_unit);
}
if(rsta & ISAC_RSTA_RAB) /* ReceiveABorted */
{
error++;
NDBGL1(L1_I_ERR, "unit %d: Receive Aborted error", sc->sc_unit);
}
if(error == 0)
NDBGL1(L1_I_ERR, "unit %d: RME unknown error, RSTA = 0x%02x!", sc->sc_unit, rsta);
i4b_Dfreembuf(sc->sc_ibuf);
c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES;
sc->sc_ibuf = NULL;
sc->sc_ib = NULL;
sc->sc_ilen = 0;
ISAC_WRITE(I_CMDR, ISAC_CMDR_RMC|ISAC_CMDR_RRES);
ISACCMDRWRDELAY();
return;
}
rest = (ISAC_READ(I_RBCL) & (ISAC_FIFO_LEN-1));
if(rest == 0)
rest = ISAC_FIFO_LEN;
if(sc->sc_ibuf == NULL)
{
if((sc->sc_ibuf = i4b_Dgetmbuf(rest)) != NULL)
sc->sc_ib = sc->sc_ibuf->m_data;
else
panic("ifpnp_isac_irq: RME, i4b_Dgetmbuf returns NULL!\n");
sc->sc_ilen = 0;
}
if(sc->sc_ilen <= (MAX_DFRAME_LEN - rest))
{
ISAC_RDFIFO(sc->sc_ib, rest);
sc->sc_ilen += rest;
sc->sc_ibuf->m_pkthdr.len =
sc->sc_ibuf->m_len = sc->sc_ilen;
if(sc->sc_trace & TRACE_D_RX)
{
i4b_trace_hdr_t hdr;
hdr.unit = L0IFPNPUNIT(sc->sc_unit);
hdr.type = TRC_CH_D;
hdr.dir = FROM_NT;
hdr.count = ++sc->sc_trace_dcount;
MICROTIME(hdr.time);
i4b_l1_trace_ind(&hdr, sc->sc_ibuf->m_len, sc->sc_ibuf->m_data);
}
c |= ISAC_CMDR_RMC;
if(sc->sc_enabled &&
(ctrl_desc[sc->sc_unit].protocol != PROTOCOL_D64S))
{
i4b_l1_ph_data_ind(L0IFPNPUNIT(sc->sc_unit), sc->sc_ibuf);
}
else
{
i4b_Dfreembuf(sc->sc_ibuf);
}
}
else
{
NDBGL1(L1_I_ERR, "RME, input buffer overflow!");
i4b_Dfreembuf(sc->sc_ibuf);
c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES;
}
sc->sc_ibuf = NULL;
sc->sc_ib = NULL;
sc->sc_ilen = 0;
}
if(ista & ISAC_ISTA_RPF) /* receive fifo full */
{
if(sc->sc_ibuf == NULL)
{
if((sc->sc_ibuf = i4b_Dgetmbuf(MAX_DFRAME_LEN)) != NULL)
sc->sc_ib= sc->sc_ibuf->m_data;
else
panic("ifpnp_isac_irq: RPF, i4b_Dgetmbuf returns NULL!\n");
sc->sc_ilen = 0;
}
if(sc->sc_ilen <= (MAX_DFRAME_LEN - ISAC_FIFO_LEN))
{
ISAC_RDFIFO(sc->sc_ib, ISAC_FIFO_LEN);
sc->sc_ilen += ISAC_FIFO_LEN;
sc->sc_ib += ISAC_FIFO_LEN;
c |= ISAC_CMDR_RMC;
}
else
{
NDBGL1(L1_I_ERR, "RPF, input buffer overflow!");
i4b_Dfreembuf(sc->sc_ibuf);
sc->sc_ibuf = NULL;
sc->sc_ib = NULL;
sc->sc_ilen = 0;
c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES;
}
}
if(ista & ISAC_ISTA_XPR) /* transmit fifo empty (XPR bit set) */
{
if((sc->sc_obuf2 != NULL) && (sc->sc_obuf == NULL))
{
sc->sc_freeflag = sc->sc_freeflag2;
sc->sc_obuf = sc->sc_obuf2;
sc->sc_op = sc->sc_obuf->m_data;
sc->sc_ol = sc->sc_obuf->m_len;
sc->sc_obuf2 = NULL;
#ifdef NOTDEF
kprintf("ob2=%x, op=%x, ol=%d, f=%d #",
sc->sc_obuf,
sc->sc_op,
sc->sc_ol,
sc->sc_state);
#endif
}
else
{
#ifdef NOTDEF
kprintf("ob=%x, op=%x, ol=%d, f=%d #",
sc->sc_obuf,
sc->sc_op,
sc->sc_ol,
sc->sc_state);
#endif
}
if(sc->sc_obuf)
{
ISAC_WRFIFO(sc->sc_op, min(sc->sc_ol, ISAC_FIFO_LEN));
if(sc->sc_ol > ISAC_FIFO_LEN) /* length > 32 ? */
{
sc->sc_op += ISAC_FIFO_LEN; /* bufferptr+32 */
sc->sc_ol -= ISAC_FIFO_LEN; /* length - 32 */
c |= ISAC_CMDR_XTF; /* set XTF bit */
}
else
{
if(sc->sc_freeflag)
{
i4b_Dfreembuf(sc->sc_obuf);
sc->sc_freeflag = 0;
}
sc->sc_obuf = NULL;
sc->sc_op = NULL;
sc->sc_ol = 0;
c |= ISAC_CMDR_XTF | ISAC_CMDR_XME;
}
}
else
{
sc->sc_state &= ~ISAC_TX_ACTIVE;
}
}
if(ista & ISAC_ISTA_CISQ) /* channel status change CISQ */
{
u_char ci;
/* get command/indication rx register*/
ci = ISAC_READ(I_CIRR);
/* if S/Q IRQ, read SQC reg to clr SQC IRQ */
if(ci & ISAC_CIRR_SQC)
ISAC_READ(I_SQRR);
/* C/I code change IRQ (flag already cleared by CIRR read) */
if(ci & ISAC_CIRR_CIC0)
ifpnp_isac_ind_hdlr(sc, (ci >> 2) & 0xf);
}
/*---------------------------------------------------------------------------*
*
* L2 -> L1: PH-DATA-REQUEST
* =========================
*
* parms:
* token softc of physical driver
* m mbuf containing L2 frame to be sent out
* freeflag MBUF_FREE: free mbuf here after having sent
* it out
* MBUF_DONTFREE: mbuf is freed by Layer 2
* returns:
* ==0 fail, nothing sent out
* !=0 ok, frame sent out
*
*---------------------------------------------------------------------------*/
static int
isic_std_ph_data_req(isdn_layer1token token, struct mbuf *m, int freeflag)
{
struct isic_softc *sc = (struct isic_softc*)token;
u_char cmd;
int s;
if (m == NULL) /* failsafe */
return (0);
s = splnet();
if(sc->sc_I430state == ST_F3) /* layer 1 not running ? */
{
NDBGL1(L1_I_ERR, "still in state F3!");
isic_std_ph_activate_req(token);
}
if(sc->sc_state & ISAC_TX_ACTIVE)
{
if(sc->sc_obuf2 == NULL)
{
sc->sc_obuf2 = m; /* save mbuf ptr */
if(freeflag)
sc->sc_freeflag2 = 1; /* IRQ must mfree */
else
sc->sc_freeflag2 = 0; /* IRQ must not mfree */
NDBGL1(L1_I_MSG, "using 2nd ISAC TX buffer, state = %s", isic_printstate(sc));
if(sc->sc_trace & TRACE_D_TX)
{
i4b_trace_hdr hdr;
hdr.type = TRC_CH_D;
hdr.dir = FROM_TE;
hdr.count = ++sc->sc_trace_dcount;
isdn_layer2_trace_ind(&sc->sc_l2, sc->sc_l3token, &hdr, m->m_len, m->m_data);
}
splx(s);
return(1);
}
NDBGL1(L1_I_ERR, "No Space in TX FIFO, state = %s", isic_printstate(sc));
if(freeflag == MBUF_FREE)
i4b_Dfreembuf(m);
splx(s);
return (0);
}
if(sc->sc_trace & TRACE_D_TX)
{
i4b_trace_hdr hdr;
hdr.type = TRC_CH_D;
hdr.dir = FROM_TE;
hdr.count = ++sc->sc_trace_dcount;
isdn_layer2_trace_ind(&sc->sc_l2, sc->sc_l3token, &hdr, m->m_len, m->m_data);
}
sc->sc_state |= ISAC_TX_ACTIVE; /* set transmitter busy flag */
NDBGL1(L1_I_MSG, "ISAC_TX_ACTIVE set");
sc->sc_freeflag = 0; /* IRQ must NOT mfree */
ISAC_WRFIFO(m->m_data, min(m->m_len, ISAC_FIFO_LEN)); /* output to TX fifo */
if(m->m_len > ISAC_FIFO_LEN) /* message > 32 bytes ? */
{
sc->sc_obuf = m; /* save mbuf ptr */
sc->sc_op = m->m_data + ISAC_FIFO_LEN; /* ptr for irq hdl */
sc->sc_ol = m->m_len - ISAC_FIFO_LEN; /* length for irq hdl */
if(freeflag)
sc->sc_freeflag = 1; /* IRQ must mfree */
cmd = ISAC_CMDR_XTF;
}
else
{
sc->sc_obuf = NULL;
sc->sc_op = NULL;
sc->sc_ol = 0;
if(freeflag)
i4b_Dfreembuf(m);
cmd = ISAC_CMDR_XTF | ISAC_CMDR_XME;
}
ISAC_WRITE(I_CMDR, cmd);
ISACCMDRWRDELAY();
splx(s);
return(1);
}
/*---------------------------------------------------------------------------*
* isic_attach_avm_pnp - attach Fritz!Card PnP
*---------------------------------------------------------------------------*/
int
isic_attach_avm_pnp(struct isa_device *dev, unsigned int iobase2)
{
struct isic_softc *sc;
u_int v;
int unit;
unit = dev->id_unit;
sc = &isic_sc[unit];
/* this thing doesn't have an HSCX, so fake the base addresses */
/* put the unit number into the lower byte - HACK */
HSCX_A_BASE = (caddr_t)(HSCX0FAKE + unit);
HSCX_B_BASE = (caddr_t)(HSCX1FAKE + unit);
/* reset the card */
/* the Linux driver does this to clear any pending ISAC interrupts */
v = 0;
v = ISAC_READ(I_STAR);
v = ISAC_READ(I_MODE);
v = ISAC_READ(I_ADF2);
v = ISAC_READ(I_ISTA);
if (v & ISAC_ISTA_EXI)
{
v = ISAC_READ(I_EXIR);
}
v = ISAC_READ(I_CIRR);
ISAC_WRITE(I_MASK, 0xff);
/* the Linux driver does this to clear any pending HSCX interrupts */
v = hscx_read_reg(0, HSCX_STAT, sc);
v = hscx_read_reg(0, HSCX_STAT+1, sc);
v = hscx_read_reg(0, HSCX_STAT+2, sc);
v = hscx_read_reg(0, HSCX_STAT+3, sc);
v = hscx_read_reg(1, HSCX_STAT, sc);
v = hscx_read_reg(1, HSCX_STAT+1, sc);
v = hscx_read_reg(1, HSCX_STAT+2, sc);
v = hscx_read_reg(1, HSCX_STAT+3, sc);
outb(sc->sc_port + STAT0_OFFSET, ASL_RESET_ALL|ASL_TIMERDISABLE);
DELAY(SEC_DELAY/100); /* 10 ms */
outb(sc->sc_port + STAT0_OFFSET, ASL_TIMERRESET|ASL_ENABLE_INT|ASL_TIMERDISABLE);
DELAY(SEC_DELAY/100); /* 10 ms */
outb(sc->sc_port + STAT1_OFFSET, ASL1_ENABLE_IOM+(ffs(sc->sc_irq)-1));
DELAY(SEC_DELAY/100); /* 10 ms */
printf("isic%d: ISAC %s (IOM-%c)\n", unit,
"2085 Version A1/A2 or 2086/2186 Version 1.1",
sc->sc_bustyp == BUS_TYPE_IOM1 ? '1' : '2');
/* init the ISAC */
isic_isac_init(sc);
/* init the "HSCX" */
avm_pnp_bchannel_setup(sc->sc_unit, HSCX_CH_A, BPROT_NONE, 0);
avm_pnp_bchannel_setup(sc->sc_unit, HSCX_CH_B, BPROT_NONE, 0);
/* can't use the normal B-Channel stuff */
avm_pnp_init_linktab(sc);
/* set trace level */
sc->sc_trace = TRACE_OFF;
sc->sc_state = ISAC_IDLE;
sc->sc_ibuf = NULL;
sc->sc_ib = NULL;
sc->sc_ilen = 0;
sc->sc_obuf = NULL;
sc->sc_op = NULL;
sc->sc_ol = 0;
sc->sc_freeflag = 0;
sc->sc_obuf2 = NULL;
sc->sc_freeflag2 = 0;
#if defined(__FreeBSD__) && __FreeBSD__ >=3
callout_handle_init(&sc->sc_T3_callout);
callout_handle_init(&sc->sc_T4_callout);
#endif
/* init higher protocol layers */
MPH_Status_Ind(sc->sc_unit, STI_ATTACH, sc->sc_cardtyp);
return(0);
}
int
isic_probe_avm_pnp(struct isa_device *dev, unsigned int iobase2)
{
struct isic_softc *sc = &isic_sc[dev->id_unit];
/* check max unit range */
if(dev->id_unit >= ISIC_MAXUNIT)
{
printf("isic%d: Error, unit %d >= ISIC_MAXUNIT for AVM Fritz! PnP\n",
dev->id_unit, dev->id_unit);
return(0);
}
sc->sc_unit = dev->id_unit;
/* check IRQ validity */
switch(ffs(dev->id_irq) - 1)
{
case 3:
case 4:
case 5:
case 7:
case 10:
case 11:
case 12:
case 15:
break;
default:
printf("isic%d: Error, invalid IRQ [%d] specified for AVM Fritz! PnP!\n",
dev->id_unit, ffs(dev->id_irq)-1);
return(0);
break;
}
sc->sc_irq = dev->id_irq;
dev->id_intr = (inthand2_t *) avm_pnp_intr;
/* check if memory addr specified */
if(dev->id_maddr)
{
printf("isic%d: Error, mem addr 0x%lx specified for AVM Fritz! PnP!\n",
dev->id_unit, (u_long)dev->id_maddr);
return(0);
}
dev->id_msize = 0;
/* check if we got an iobase */
if(!((dev->id_iobase >= 0x160) && (dev->id_iobase <= 0x360)))
{
printf("isic%d: Error, invalid iobase 0x%x specified for AVM Fritz! PnP!\n",
dev->id_unit, dev->id_iobase);
return(0);
}
sc->sc_port = dev->id_iobase;
/* setup access routines */
sc->clearirq = NULL;
sc->readreg = avm_pnp_read_reg;
sc->writereg = avm_pnp_write_reg;
sc->readfifo = avm_pnp_read_fifo;
sc->writefifo = avm_pnp_write_fifo;
/* setup card type */
sc->sc_cardtyp = CARD_TYPEP_AVM_PNP;
/* setup IOM bus type */
sc->sc_bustyp = BUS_TYPE_IOM2;
sc->sc_ipac = 0;
sc->sc_bfifolen = HSCX_FIFO_LEN;
/* the ISAC lives at offset 0x10, but we can't use that. */
/* instead, put the unit number into the lower byte - HACK */
ISAC_BASE = (caddr_t)((int)(dev->id_iobase & ~0xff) + dev->id_unit);
outb(sc->sc_port + STAT0_OFFSET, ASL_RESET_ALL|ASL_TIMERDISABLE);
ISAC_WRITE(I_MASK, 0x0);
outb(sc->sc_port + STAT0_OFFSET, ASL_TIMERRESET|ASL_ENABLE_INT|ASL_TIMERDISABLE);
ISAC_WRITE(I_MASK, 0x41);
return (1);
}
/*---------------------------------------------------------------------------*
* isic - device driver interrupt routine
*---------------------------------------------------------------------------*/
void
isicintr(struct l1_softc *sc)
{
if(sc->sc_ipac == 0) /* HSCX/ISAC interupt routine */
{
u_char was_hscx_irq = 0;
u_char was_isac_irq = 0;
register u_char hscx_irq_stat;
register u_char isac_irq_stat;
for(;;)
{
/* get hscx irq status from hscx b ista */
hscx_irq_stat =
HSCX_READ(HSCX_CH_B, H_ISTA) & ~HSCX_B_IMASK;
/* get isac irq status */
isac_irq_stat = ISAC_READ(I_ISTA);
/* do as long as there are pending irqs in the chips */
if(!hscx_irq_stat && !isac_irq_stat)
break;
if(hscx_irq_stat & (HSCX_ISTA_RME | HSCX_ISTA_RPF |
HSCX_ISTA_RSC | HSCX_ISTA_XPR |
HSCX_ISTA_TIN | HSCX_ISTA_EXB))
{
isic_hscx_irq(sc, hscx_irq_stat,
HSCX_CH_B,
hscx_irq_stat & HSCX_ISTA_EXB);
was_hscx_irq = 1;
}
if(hscx_irq_stat & (HSCX_ISTA_ICA | HSCX_ISTA_EXA))
{
isic_hscx_irq(sc,
HSCX_READ(HSCX_CH_A, H_ISTA) & ~HSCX_A_IMASK,
HSCX_CH_A,
hscx_irq_stat & HSCX_ISTA_EXA);
was_hscx_irq = 1;
}
if(isac_irq_stat)
{
isic_isac_irq(sc, isac_irq_stat); /* isac handler */
was_isac_irq = 1;
}
}
HSCX_WRITE(0, H_MASK, 0xff);
ISAC_WRITE(I_MASK, 0xff);
HSCX_WRITE(1, H_MASK, 0xff);
#ifdef ELSA_QS1ISA
DELAY(80);
if((sc->sc_cardtyp == CARD_TYPEP_ELSAQS1ISA) && (sc->clearirq))
{
sc->clearirq(sc);
}
#else
DELAY(100);
#endif
HSCX_WRITE(0, H_MASK, HSCX_A_IMASK);
ISAC_WRITE(I_MASK, ISAC_IMASK);
HSCX_WRITE(1, H_MASK, HSCX_B_IMASK);
}
else /* IPAC interrupt routine */
{
register u_char ipac_irq_stat;
register u_char was_ipac_irq = 0;
for(;;)
{
/* get global irq status */
ipac_irq_stat = (IPAC_READ(IPAC_ISTA)) & 0x3f;
/* check hscx a */
if(ipac_irq_stat & (IPAC_ISTA_ICA | IPAC_ISTA_EXA))
{
/* HSCX A interrupt */
isic_hscx_irq(sc, HSCX_READ(HSCX_CH_A, H_ISTA),
HSCX_CH_A,
ipac_irq_stat & IPAC_ISTA_EXA);
was_ipac_irq = 1;
}
if(ipac_irq_stat & (IPAC_ISTA_ICB | IPAC_ISTA_EXB))
{
/* HSCX B interrupt */
isic_hscx_irq(sc, HSCX_READ(HSCX_CH_B, H_ISTA),
HSCX_CH_B,
ipac_irq_stat & IPAC_ISTA_EXB);
was_ipac_irq = 1;
}
if(ipac_irq_stat & IPAC_ISTA_ICD)
{
/* ISAC interrupt */
isic_isac_irq(sc, ISAC_READ(I_ISTA));
was_ipac_irq = 1;
}
if(ipac_irq_stat & IPAC_ISTA_EXD)
{
/* force ISAC interrupt handling */
isic_isac_irq(sc, ISAC_ISTA_EXI);
was_ipac_irq = 1;
}
/* do as long as there are pending irqs in the chip */
if(!ipac_irq_stat)
break;
}
IPAC_WRITE(IPAC_MASK, 0xff);
DELAY(50);
IPAC_WRITE(IPAC_MASK, 0xc0);
}
}
/*---------------------------------------------------------------------------*
* L1 ISAC initialization
*---------------------------------------------------------------------------*/
int
isic_isac_init(struct isic_softc *sc)
{
ISAC_IMASK = 0xff; /* disable all irqs */
ISAC_WRITE(I_MASK, ISAC_IMASK);
if(sc->sc_bustyp != BUS_TYPE_IOM2)
{
NDBGL1(L1_I_SETUP, "configuring for IOM-1 mode");
/* ADF2: Select mode IOM-1 */
ISAC_WRITE(I_ADF2, 0x00);
/* SPCR: serial port control register:
* SPU - software power up = 0
* SAC - SIP port high Z
* SPM - timing mode 0
* TLP - test loop = 0
* C1C, C2C - B1 and B2 switched to/from SPa
*/
ISAC_WRITE(I_SPCR, ISAC_SPCR_C1C1|ISAC_SPCR_C2C1);
/* SQXR: S/Q channel xmit register:
* SQIE - S/Q IRQ enable = 0
* SQX1-4 - Fa bits = 1
*/
ISAC_WRITE(I_SQXR, ISAC_SQXR_SQX1|ISAC_SQXR_SQX2|ISAC_SQXR_SQX3|ISAC_SQXR_SQX4);
/* ADF1: additional feature reg 1:
* WTC - watchdog = 0
* TEM - test mode = 0
* PFS - pre-filter = 0
* CFS - IOM clock/frame always active
* FSC1/2 - polarity of 8kHz strobe
* ITF - interframe fill = idle
*/
ISAC_WRITE(I_ADF1, ISAC_ADF1_FC2); /* ADF1 */
/* STCR: sync transfer control reg:
* TSF - terminal secific functions = 0
* TBA - TIC bus address = 7
* STx/SCx = 0
*/
ISAC_WRITE(I_STCR, ISAC_STCR_TBA2|ISAC_STCR_TBA1|ISAC_STCR_TBA0);
}
else
{
NDBGL1(L1_I_SETUP, "configuring for IOM-2 mode");
/* ADF2: Select mode IOM-2 */
ISAC_WRITE(I_ADF2, ISAC_ADF2_IMS);
/* SPCR: serial port control register:
* SPU - software power up = 0
* SPM - timing mode 0
* TLP - test loop = 0
* C1C, C2C - B1 + C1 and B2 + IC2 monitoring
*/
ISAC_WRITE(I_SPCR, 0x00);
/* SQXR: S/Q channel xmit register:
* IDC - IOM direction = 0 (master)
* CFS - Config Select = 0 (clock always active)
* CI1E - C/I channel 1 IRQ enable = 0
* SQIE - S/Q IRQ enable = 0
* SQX1-4 - Fa bits = 1
*/
ISAC_WRITE(I_SQXR, ISAC_SQXR_SQX1|ISAC_SQXR_SQX2|ISAC_SQXR_SQX3|ISAC_SQXR_SQX4);
/* ADF1: additional feature reg 1:
* WTC - watchdog = 0
* TEM - test mode = 0
* PFS - pre-filter = 0
* IOF - IOM i/f off = 0
* ITF - interframe fill = idle
*/
ISAC_WRITE(I_ADF1, 0x00);
/* STCR: sync transfer control reg:
* TSF - terminal secific functions = 0
* TBA - TIC bus address = 7
* STx/SCx = 0
*/
ISAC_WRITE(I_STCR, ISAC_STCR_TBA2|ISAC_STCR_TBA1|ISAC_STCR_TBA0);
}
/* MODE: Mode Register:
* MDSx - transparent mode 2
* TMD - timer mode = external
* RAC - Receiver enabled
* DIMx - digital i/f mode
*/
ISAC_WRITE(I_MODE, ISAC_MODE_MDS2|ISAC_MODE_MDS1|ISAC_MODE_RAC|ISAC_MODE_DIM0);
/* enabled interrupts:
* ===================
* RME - receive message end
* RPF - receive pool full
* XPR - transmit pool ready
* CISQ - CI or S/Q channel change
* EXI - extended interrupt
*/
ISAC_IMASK = ISAC_MASK_RSC | /* auto mode only */
ISAC_MASK_TIN | /* timer irq */
ISAC_MASK_SIN; /* sync xfer irq */
ISAC_WRITE(I_MASK, ISAC_IMASK);
ISAC_WRITE(I_CMDR, ISAC_CMDR_RRES|ISAC_CMDR_XRES);
ISACCMDRWRDELAY();
return(0);
}
/*---------------------------------------------------------------------------*
* ISACSX interrupt service routine
*---------------------------------------------------------------------------*/
void
isic_isacsx_irq(struct isic_softc *sc, int ista)
{
register u_char c = 0;
register u_char istad = 0;
NDBGL1(L1_F_MSG, "%s: ista = 0x%02x", device_xname(&sc->sc_dev), ista);
/* was it an HDLC interrupt ? */
if (ista & ISACSX_ISTA_ICD)
{
istad = ISAC_READ(I_ISTAD);
NDBGL1(L1_F_MSG, "%s: istad = 0x%02x", device_xname(&sc->sc_dev), istad);
if(istad & (ISACSX_ISTAD_RFO|ISACSX_ISTAD_XMR|ISACSX_ISTAD_XDU))
{
/* not really EXIR, but very similar */
c |= isic_isacsx_exir_hdlr(sc, istad);
}
}
if(istad & ISACSX_ISTAD_RME) /* receive message end */
{
register int rest;
u_char rsta;
/* get rx status register */
rsta = ISAC_READ(I_RSTAD);
/* Check for Frame and CRC valid */
if((rsta & ISACSX_RSTAD_MASK) != (ISACSX_RSTAD_VFR|ISACSX_RSTAD_CRC))
{
int error = 0;
if(!(rsta & ISACSX_RSTAD_VFR)) /* VFR error */
{
error++;
NDBGL1(L1_I_ERR, "%s: Frame not valid error", device_xname(&sc->sc_dev));
}
if(!(rsta & ISACSX_RSTAD_CRC)) /* CRC error */
{
error++;
NDBGL1(L1_I_ERR, "%s: CRC error", device_xname(&sc->sc_dev));
}
if(rsta & ISACSX_RSTAD_RDO) /* ReceiveDataOverflow */
{
error++;
NDBGL1(L1_I_ERR, "%s: Data Overrun error", device_xname(&sc->sc_dev));
}
if(rsta & ISACSX_RSTAD_RAB) /* ReceiveABorted */
{
error++;
NDBGL1(L1_I_ERR, "%s: Receive Aborted error", device_xname(&sc->sc_dev));
}
if(error == 0)
NDBGL1(L1_I_ERR, "%s: RME unknown error, RSTAD = 0x%02x!", device_xname(&sc->sc_dev), rsta);
i4b_Dfreembuf(sc->sc_ibuf);
c |= ISACSX_CMDRD_RMC|ISACSX_CMDRD_RRES;
sc->sc_ibuf = NULL;
sc->sc_ib = NULL;
sc->sc_ilen = 0;
ISAC_WRITE(I_CMDRD, ISACSX_CMDRD_RMC|ISACSX_CMDRD_RRES);
return;
}
rest = (ISAC_READ(I_RBCLD) & (ISACSX_FIFO_LEN-1));
if(rest == 0)
rest = ISACSX_FIFO_LEN;
if(sc->sc_ibuf == NULL)
{
if((sc->sc_ibuf = i4b_Dgetmbuf(rest)) != NULL)
sc->sc_ib = sc->sc_ibuf->m_data;
else
panic("isic_isacsx_irq: RME, i4b_Dgetmbuf returns NULL!\n");
sc->sc_ilen = 0;
}
if(sc->sc_ilen <= (MAX_DFRAME_LEN - rest))
{
ISAC_RDFIFO(sc->sc_ib, rest);
/* the last byte contains status, strip it */
sc->sc_ilen += rest - 1;
sc->sc_ibuf->m_pkthdr.len =
sc->sc_ibuf->m_len = sc->sc_ilen;
if(sc->sc_trace & TRACE_D_RX)
{
i4b_trace_hdr hdr;
memset(&hdr, 0, sizeof hdr);
hdr.type = TRC_CH_D;
hdr.dir = FROM_NT;
hdr.count = ++sc->sc_trace_dcount;
isdn_layer2_trace_ind(&sc->sc_l2, sc->sc_l3token, &hdr, sc->sc_ibuf->m_len, sc->sc_ibuf->m_data);
}
c |= ISACSX_CMDRD_RMC;
if(sc->sc_intr_valid == ISIC_INTR_VALID &&
(((struct isdn_l3_driver*)sc->sc_l3token)->protocol != PROTOCOL_D64S))
{
isdn_layer2_data_ind(&sc->sc_l2, sc->sc_l3token, sc->sc_ibuf);
}
else
{
i4b_Dfreembuf(sc->sc_ibuf);
}
}
else
{
NDBGL1(L1_I_ERR, "RME, input buffer overflow!");
i4b_Dfreembuf(sc->sc_ibuf);
c |= ISACSX_CMDRD_RMC|ISACSX_CMDRD_RRES;
}
sc->sc_ibuf = NULL;
sc->sc_ib = NULL;
sc->sc_ilen = 0;
}
if(istad & ISACSX_ISTAD_RPF) /* receive fifo full */
{
if(sc->sc_ibuf == NULL)
{
if((sc->sc_ibuf = i4b_Dgetmbuf(MAX_DFRAME_LEN)) != NULL)
sc->sc_ib= sc->sc_ibuf->m_data;
else
panic("isic_isacsx_irq: RPF, i4b_Dgetmbuf returns NULL!\n");
sc->sc_ilen = 0;
}
if(sc->sc_ilen <= (MAX_DFRAME_LEN - ISACSX_FIFO_LEN))
{
ISAC_RDFIFO(sc->sc_ib, ISACSX_FIFO_LEN);
sc->sc_ilen += ISACSX_FIFO_LEN;
sc->sc_ib += ISACSX_FIFO_LEN;
c |= ISACSX_CMDRD_RMC;
}
else
{
NDBGL1(L1_I_ERR, "RPF, input buffer overflow!");
i4b_Dfreembuf(sc->sc_ibuf);
sc->sc_ibuf = NULL;
sc->sc_ib = NULL;
sc->sc_ilen = 0;
c |= ISACSX_CMDRD_RMC|ISACSX_CMDRD_RRES;
}
}
if(istad & ISACSX_ISTAD_XPR) /* transmit fifo empty (XPR bit set) */
{
if((sc->sc_obuf2 != NULL) && (sc->sc_obuf == NULL))
{
sc->sc_freeflag = sc->sc_freeflag2;
sc->sc_obuf = sc->sc_obuf2;
sc->sc_op = sc->sc_obuf->m_data;
sc->sc_ol = sc->sc_obuf->m_len;
sc->sc_obuf2 = NULL;
#ifdef NOTDEF
printf("ob2=%x, op=%x, ol=%d, f=%d #",
sc->sc_obuf,
sc->sc_op,
sc->sc_ol,
sc->sc_state);
#endif
}
else
{
#ifdef NOTDEF
printf("ob=%x, op=%x, ol=%d, f=%d #",
sc->sc_obuf,
sc->sc_op,
sc->sc_ol,
sc->sc_state);
#endif
}
if(sc->sc_obuf)
{
ISAC_WRFIFO(sc->sc_op, min(sc->sc_ol, ISACSX_FIFO_LEN));
if(sc->sc_ol > ISACSX_FIFO_LEN) /* length > 32 ? */
{
sc->sc_op += ISACSX_FIFO_LEN; /* bufferptr+32 */
sc->sc_ol -= ISACSX_FIFO_LEN; /* length - 32 */
c |= ISACSX_CMDRD_XTF; /* set XTF bit */
}
else
{
if(sc->sc_freeflag)
{
i4b_Dfreembuf(sc->sc_obuf);
sc->sc_freeflag = 0;
}
sc->sc_obuf = NULL;
sc->sc_op = NULL;
sc->sc_ol = 0;
c |= ISACSX_CMDRD_XTF | ISACSX_CMDRD_XME;
}
}
else
{
sc->sc_state &= ~ISAC_TX_ACTIVE;
}
}
if(ista & ISACSX_ISTA_CIC) /* channel status change CISQ */
{
register u_char ci;
/* get command/indication rx register*/
ci = ISAC_READ(I_CIR0);
/* C/I code change IRQ (flag already cleared by CIR0 read) */
if(ci & ISACSX_CIR0_CIC0)
isic_isacsx_ind_hdlr(sc, (ci >> 4) & 0xf);
}
if(c)
{
ISAC_WRITE(I_CMDRD, c);
}
}
/*---------------------------------------------------------------------------*
* isic - device driver interrupt routine
*---------------------------------------------------------------------------*/
int
isicintr(void *arg)
{
struct isic_softc *sc = arg;
/* could this be an interrupt for us? */
if (sc->sc_intr_valid == ISIC_INTR_DYING)
return 0; /* do not touch removed hardware */
if(sc->sc_ipac == 0) /* HSCX/ISAC interupt routine */
{
u_char was_hscx_irq = 0;
u_char was_isac_irq = 0;
register u_char hscx_irq_stat;
register u_char isac_irq_stat;
for(;;)
{
/* get hscx irq status from hscx b ista */
hscx_irq_stat =
HSCX_READ(HSCX_CH_B, H_ISTA) & ~HSCX_B_IMASK;
/* get isac irq status */
isac_irq_stat = ISAC_READ(I_ISTA);
/* do as long as there are pending irqs in the chips */
if(!hscx_irq_stat && !isac_irq_stat)
break;
if(hscx_irq_stat & (HSCX_ISTA_RME | HSCX_ISTA_RPF |
HSCX_ISTA_RSC | HSCX_ISTA_XPR |
HSCX_ISTA_TIN | HSCX_ISTA_EXB))
{
isic_hscx_irq(sc, hscx_irq_stat,
HSCX_CH_B,
hscx_irq_stat & HSCX_ISTA_EXB);
was_hscx_irq = 1;
}
if(hscx_irq_stat & (HSCX_ISTA_ICA | HSCX_ISTA_EXA))
{
isic_hscx_irq(sc,
HSCX_READ(HSCX_CH_A, H_ISTA) & ~HSCX_A_IMASK,
HSCX_CH_A,
hscx_irq_stat & HSCX_ISTA_EXA);
was_hscx_irq = 1;
}
if(isac_irq_stat)
{
/* isac handler */
isic_isac_irq(sc, isac_irq_stat);
was_isac_irq = 1;
}
}
HSCX_WRITE(0, H_MASK, 0xff);
ISAC_WRITE(I_MASK, 0xff);
HSCX_WRITE(1, H_MASK, 0xff);
if (sc->clearirq)
{
DELAY(80);
sc->clearirq(sc);
} else
DELAY(100);
HSCX_WRITE(0, H_MASK, HSCX_A_IMASK);
ISAC_WRITE(I_MASK, ISAC_IMASK);
HSCX_WRITE(1, H_MASK, HSCX_B_IMASK);
return(was_hscx_irq || was_isac_irq);
}
else /* IPAC interrupt routine */
{
register u_char ipac_irq_stat;
register u_char was_ipac_irq = 0;
for(;;)
{
/* get global irq status */
ipac_irq_stat = (IPAC_READ(IPAC_ISTA)) & 0x3f;
/* check hscx a */
if(ipac_irq_stat & (IPAC_ISTA_ICA | IPAC_ISTA_EXA))
{
/* HSCX A interrupt */
isic_hscx_irq(sc, HSCX_READ(HSCX_CH_A, H_ISTA),
HSCX_CH_A,
ipac_irq_stat & IPAC_ISTA_EXA);
was_ipac_irq = 1;
}
if(ipac_irq_stat & (IPAC_ISTA_ICB | IPAC_ISTA_EXB))
{
/* HSCX B interrupt */
isic_hscx_irq(sc, HSCX_READ(HSCX_CH_B, H_ISTA),
HSCX_CH_B,
ipac_irq_stat & IPAC_ISTA_EXB);
was_ipac_irq = 1;
}
if(ipac_irq_stat & IPAC_ISTA_ICD)
{
/* ISAC interrupt, Obey ISAC-IPAC differences */
u_int8_t isac_ista = ISAC_READ(I_ISTA);
if (isac_ista & 0xfe)
isic_isac_irq(sc, isac_ista & 0xfe);
if (isac_ista & 0x01) /* unexpected */
printf("%s: unexpected ipac timer2 irq\n",
sc->sc_dev.dv_xname);
was_ipac_irq = 1;
}
if(ipac_irq_stat & IPAC_ISTA_EXD)
{
/* ISAC EXI interrupt */
isic_isac_irq(sc, ISAC_ISTA_EXI);
was_ipac_irq = 1;
}
/* do as long as there are pending irqs in the chip */
if(!ipac_irq_stat)
break;
}
#if 0
/*
* This seems not to be necessary on IPACs - no idea why
* it is here - but due to limit range of test cards, leave
* it in for now, in case we have to resurrect it.
*/
IPAC_WRITE(IPAC_MASK, 0xff);
DELAY(50);
IPAC_WRITE(IPAC_MASK, 0xc0);
#endif
return(was_ipac_irq);
}
}
