u32 ath9k_regd_get_ctl(struct ath_hal *ah, struct ath9k_channel *chan)
{
u32 ctl = NO_CTL;
struct ath9k_channel *ichan;
if (ah->ah_countryCode == CTRY_DEFAULT && isWwrSKU(ah)) {
if (IS_CHAN_B(chan))
ctl = SD_NO_CTL | CTL_11B;
else if (IS_CHAN_G(chan))
ctl = SD_NO_CTL | CTL_11G;
else
ctl = SD_NO_CTL | CTL_11A;
} else {
ichan = ath9k_regd_check_channel(ah, chan);
if (ichan != NULL) {
/* FIXME */
if (IS_CHAN_A(ichan))
ctl = ichan->conformanceTestLimit[0];
else if (IS_CHAN_B(ichan))
ctl = ichan->conformanceTestLimit[1];
else if (IS_CHAN_G(ichan))
ctl = ichan->conformanceTestLimit[2];
if (IS_CHAN_G(chan) && (ctl & 0xf) == CTL_11B)
ctl = (ctl & ~0xf) | CTL_11G;
}
}
return ctl;
}
static void
dumpchannels(struct ath_hal *ah, int nc, HAL_CHANNEL *chans, int16_t *txpow)
{
int i;
for (i = 0; i < nc; i++) {
HAL_CHANNEL *c = &chans[i];
int type;
printf("%s%u", sep, c->channel);
if (IS_CHAN_TURBO(c))
type = 'T';
else if (IS_CHAN_A(c))
type = 'A';
else if (IS_CHAN_G(c))
type = 'G';
else
type = 'B';
if (dopassive && IS_CHAN_PASSIVE(c))
type = tolower(type);
printf("%c %d.%d", type, txpow[i]/2, (txpow[i]%2)*5);
if ((n++ % 6) == 0)
sep = "\n";
else
sep = " ";
}
}
static void
print_chaninfo(int freq, int flags)
{
printf("%u MHz", freq);
if (IS_CHAN_FHSS(flags))
printf(" FHSS");
if (IS_CHAN_A(flags)) {
if (flags & IEEE80211_CHAN_HALF)
printf(" 11a/10Mhz");
else if (flags & IEEE80211_CHAN_QUARTER)
printf(" 11a/5Mhz");
else
printf(" 11a");
}
if (IS_CHAN_ANYG(flags)) {
if (flags & IEEE80211_CHAN_HALF)
printf(" 11g/10Mhz");
else if (flags & IEEE80211_CHAN_QUARTER)
printf(" 11g/5Mhz");
else
printf(" 11g");
} else if (IS_CHAN_B(flags))
printf(" 11b");
if (flags & IEEE80211_CHAN_TURBO)
printf(" Turbo");
if (flags & IEEE80211_CHAN_HT20)
printf(" ht/20");
else if (flags & IEEE80211_CHAN_HT40D)
printf(" ht/40-");
else if (flags & IEEE80211_CHAN_HT40U)
printf(" ht/40+");
printf(" ");
}
static HAL_BOOL
ar2133GetChannelMaxMinPower(struct ath_hal *ah,
const struct ieee80211_channel *chan,
int16_t *maxPow, int16_t *minPow)
{
#if 0
struct ath_hal_5212 *ahp = AH5212(ah);
int numChannels=0,i,last;
int totalD, totalF,totalMin;
EXPN_DATA_PER_CHANNEL_5112 *data=AH_NULL;
EEPROM_POWER_EXPN_5112 *powerArray=AH_NULL;
*maxPow = 0;
if (IS_CHAN_A(chan)) {
powerArray = ahp->ah_modePowerArray5112;
data = powerArray[headerInfo11A].pDataPerChannel;
numChannels = powerArray[headerInfo11A].numChannels;
} else if (IS_CHAN_G(chan) || IS_CHAN_108G(chan)) {
/* XXX - is this correct? Should we also use the same power for turbo G? */
powerArray = ahp->ah_modePowerArray5112;
data = powerArray[headerInfo11G].pDataPerChannel;
numChannels = powerArray[headerInfo11G].numChannels;
} else if (IS_CHAN_B(chan)) {
powerArray = ahp->ah_modePowerArray5112;
data = powerArray[headerInfo11B].pDataPerChannel;
numChannels = powerArray[headerInfo11B].numChannels;
} else {
return (AH_TRUE);
}
/* Make sure the channel is in the range of the TP values
* (freq piers)
*/
if ((numChannels < 1) ||
(chan->channel < data[0].channelValue) ||
(chan->channel > data[numChannels-1].channelValue))
return(AH_FALSE);
/* Linearly interpolate the power value now */
for (last=0,i=0;
(i<numChannels) && (chan->channel > data[i].channelValue);
last=i++);
totalD = data[i].channelValue - data[last].channelValue;
if (totalD > 0) {
totalF = data[i].maxPower_t4 - data[last].maxPower_t4;
*maxPow = (int8_t) ((totalF*(chan->channel-data[last].channelValue) + data[last].maxPower_t4*totalD)/totalD);
totalMin = ar2133GetMinPower(ah,&data[i]) - ar2133GetMinPower(ah, &data[last]);
*minPow = (int8_t) ((totalMin*(chan->channel-data[last].channelValue) + ar2133GetMinPower(ah, &data[last])*totalD)/totalD);
return (AH_TRUE);
} else {
if (chan->channel == data[i].channelValue) {
*maxPow = data[i].maxPower_t4;
*minPow = ar2133GetMinPower(ah, &data[i]);
return(AH_TRUE);
} else
return(AH_FALSE);
}
#else
*maxPow = *minPow = 0;
return AH_FALSE;
#endif
}
/*
* Reads EEPROM header info from device structure and programs
* all rf registers
*
* REQUIRES: Access to the analog rf device
*/
static HAL_BOOL
ar5111SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
u_int16_t modesIndex, u_int16_t *rfXpdGain)
{
struct ath_hal_5212 *ahp = AH5212(ah);
u_int16_t rfXpdGainFixed, rfPloSel, rfPwdXpd, gainI;
u_int16_t tempOB, tempDB;
u_int32_t ob2GHz, db2GHz, rfReg[N(ar5212Bank6_5111)];
int i, regWrites = 0;
/* Setup rf parameters */
switch (chan->channelFlags & CHANNEL_ALL) {
case CHANNEL_A:
case CHANNEL_T:
if (4000 < chan->channel && chan->channel < 5260) {
tempOB = ahp->ah_ob1;
tempDB = ahp->ah_db1;
} else if (5260 <= chan->channel && chan->channel < 5500) {
tempOB = ahp->ah_ob2;
tempDB = ahp->ah_db2;
} else if (5500 <= chan->channel && chan->channel < 5725) {
tempOB = ahp->ah_ob3;
tempDB = ahp->ah_db3;
} else if (chan->channel >= 5725) {
tempOB = ahp->ah_ob4;
tempDB = ahp->ah_db4;
} else {
/* XXX when does this happen??? */
tempOB = tempDB = 0;
}
ob2GHz = db2GHz = 0;
rfXpdGainFixed = ahp->ah_xgain[headerInfo11A];
rfPloSel = ahp->ah_xpd[headerInfo11A];
rfPwdXpd = !ahp->ah_xpd[headerInfo11A];
gainI = ahp->ah_gainI[headerInfo11A];
break;
case CHANNEL_B:
tempOB = ahp->ah_obFor24;
tempDB = ahp->ah_dbFor24;
ob2GHz = ahp->ah_ob2GHz[0];
db2GHz = ahp->ah_db2GHz[0];
rfXpdGainFixed = ahp->ah_xgain[headerInfo11B];
rfPloSel = ahp->ah_xpd[headerInfo11B];
rfPwdXpd = !ahp->ah_xpd[headerInfo11B];
gainI = ahp->ah_gainI[headerInfo11B];
break;
case CHANNEL_G:
tempOB = ahp->ah_obFor24g;
tempDB = ahp->ah_dbFor24g;
ob2GHz = ahp->ah_ob2GHz[1];
db2GHz = ahp->ah_db2GHz[1];
rfXpdGainFixed = ahp->ah_xgain[headerInfo11G];
rfPloSel = ahp->ah_xpd[headerInfo11G];
rfPwdXpd = !ahp->ah_xpd[headerInfo11G];
gainI = ahp->ah_gainI[headerInfo11G];
break;
default:
HDPRINTF(ah, HAL_DBG_CHANNEL, "%s: invalid channel flags 0x%x\n",
__func__, chan->channelFlags);
return AH_FALSE;
}
HALASSERT(1 <= tempOB && tempOB <= 5);
HALASSERT(1 <= tempDB && tempDB <= 5);
/* Bank 0 Write */
for (i = 0; i < N(ar5212Bank0_5111); i++)
rfReg[i] = ar5212Bank0_5111[i][modesIndex];
if (IS_CHAN_2GHZ(chan)) {
ar5212ModifyRfBuffer(rfReg, ob2GHz, 3, 119, 0);
ar5212ModifyRfBuffer(rfReg, db2GHz, 3, 122, 0);
}
for (i = 0; i < N(ar5212Bank0_5111); i++) {
OS_REG_WRITE(ah, ar5212Bank0_5111[i][0], rfReg[i]);
ALLOW_DMA_READ_COMPLETE(regWrites);
}
/* Bank 1 Write */
REG_WRITE_ARRAY(ar5212Bank1_5111, 1, regWrites);
/* Bank 2 Write */
REG_WRITE_ARRAY(ar5212Bank2_5111, modesIndex, regWrites);
/* Bank 3 Write */
REG_WRITE_ARRAY(ar5212Bank3_5111, modesIndex, regWrites);
/* Bank 6 Write */
for (i = 0; i < N(ar5212Bank6_5111); i++)
rfReg[i] = ar5212Bank6_5111[i][modesIndex];
if (IS_CHAN_A(chan)) { /* NB: CHANNEL_A | CHANNEL_T */
ar5212ModifyRfBuffer(rfReg, ahp->ah_cornerCal.pd84, 1, 51, 3);
ar5212ModifyRfBuffer(rfReg, ahp->ah_cornerCal.pd90, 1, 45, 3);
}
ar5212ModifyRfBuffer(rfReg, rfPwdXpd, 1, 95, 0);
ar5212ModifyRfBuffer(rfReg, rfXpdGainFixed, 4, 96, 0);
/* Set 5212 OB & DB */
ar5212ModifyRfBuffer(rfReg, tempOB, 3, 104, 0);
ar5212ModifyRfBuffer(rfReg, tempDB, 3, 107, 0);
for (i = 0; i < N(ar5212Bank6_5111); i++) {
OS_REG_WRITE(ah, ar5212Bank6_5111[i][0], rfReg[i]);
ALLOW_DMA_READ_COMPLETE(regWrites);
}
/* Bank 7 Write */
for (i = 0; i < N(ar5212Bank7_5111); i++)
rfReg[i] = ar5212Bank7_5111[i][modesIndex];
ar5212ModifyRfBuffer(rfReg, gainI, 6, 29, 0);
ar5212ModifyRfBuffer(rfReg, rfPloSel, 1, 4, 0);
if (IS_CHAN_QUARTER_RATE(chan) || IS_CHAN_HALF_RATE(chan)) {
u_int32_t rfWaitI, rfWaitS, rfMaxTime;
rfWaitS = 0x1f;
rfWaitI = (IS_CHAN_HALF_RATE(chan)) ? 0x10 : 0x1f;
rfMaxTime = 3;
ar5212ModifyRfBuffer(rfReg, rfWaitS, 5, 19, 0);
ar5212ModifyRfBuffer(rfReg, rfWaitI, 5, 24, 0);
ar5212ModifyRfBuffer(rfReg, rfMaxTime, 2, 49, 0);
}
for (i = 0; i < N(ar5212Bank7_5111); i++) {
OS_REG_WRITE(ah, ar5212Bank7_5111[i][0], rfReg[i]);
ALLOW_DMA_READ_COMPLETE(regWrites);
}
/* Now that we have reprogrammed rfgain value, clear the flag. */
ahp->ah_rfgainState = HAL_RFGAIN_INACTIVE;
return AH_TRUE;
}
