/**
* @brief Initialize the FSMC_NORSRAM device according to the specified
* control parameters in the FSMC_NORSRAM_InitTypeDef
* @param Device: Pointer to NORSRAM device instance
* @param Init: Pointer to NORSRAM Initialization structure
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef* Init)
{
uint32_t tmpr = 0U;
/* Check the parameters */
assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
assert_param(IS_FSMC_MUX(Init->DataAddressMux));
assert_param(IS_FSMC_MEMORY(Init->MemoryType));
assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
assert_param(IS_FSMC_PAGESIZE(Init->PageSize));
/* Get the BTCR register value */
tmpr = Device->BTCR[Init->NSBank];
/* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN,
WAITEN, EXTMOD, ASYNCWAIT, CPSIZE and CBURSTRW bits */
tmpr &= ((uint32_t)~(FSMC_BCR1_MBKEN | FSMC_BCR1_MUXEN | FSMC_BCR1_MTYP | \
FSMC_BCR1_MWID | FSMC_BCR1_FACCEN | FSMC_BCR1_BURSTEN | \
FSMC_BCR1_WAITPOL | FSMC_BCR1_WRAPMOD | FSMC_BCR1_WAITCFG | \
FSMC_BCR1_WREN | FSMC_BCR1_WAITEN | FSMC_BCR1_EXTMOD | \
FSMC_BCR1_ASYNCWAIT | FSMC_BCR1_CPSIZE | FSMC_BCR1_CBURSTRW));
/* Set NORSRAM device control parameters */
tmpr |= (uint32_t)(Init->DataAddressMux |\
Init->MemoryType |\
Init->MemoryDataWidth |\
Init->BurstAccessMode |\
Init->WaitSignalPolarity |\
Init->WrapMode |\
Init->WaitSignalActive |\
Init->WriteOperation |\
Init->WaitSignal |\
Init->ExtendedMode |\
Init->AsynchronousWait |\
Init->PageSize |\
Init->WriteBurst
);
if(Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
{
tmpr |= (uint32_t)FSMC_NORSRAM_FLASH_ACCESS_ENABLE;
}
Device->BTCR[Init->NSBank] = tmpr;
return HAL_OK;
}
/**
* @brief Initialize the FSMC_NORSRAM device according to the specified
* control parameters in the FSMC_NORSRAM_InitTypeDef
* @param Device: Pointer to NORSRAM device instance
* @param Init: Pointer to NORSRAM Initialization structure
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef* Init)
{
/* Check the parameters */
assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
assert_param(IS_FSMC_MUX(Init->DataAddressMux));
assert_param(IS_FSMC_MEMORY(Init->MemoryType));
assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
/* Disable NORSRAM Device */
__FSMC_NORSRAM_DISABLE(Device, Init->NSBank);
/* Set NORSRAM device control parameters */
if(Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
{
MODIFY_REG(Device->BTCR[Init->NSBank], \
(FSMC_BCRx_FACCEN | FSMC_BCRx_MUXEN | FSMC_BCRx_MTYP | \
FSMC_BCRx_MWID | FSMC_BCRx_BURSTEN | FSMC_BCRx_WAITPOL | FSMC_BCRx_WRAPMOD | FSMC_BCRx_WAITCFG | \
FSMC_BCRx_WREN | FSMC_BCRx_WAITEN | FSMC_BCRx_EXTMOD | FSMC_BCRx_ASYNCWAIT | FSMC_BCRx_CBURSTRW), \
(FSMC_NORSRAM_FLASH_ACCESS_ENABLE | Init->DataAddressMux | Init->MemoryType | \
Init->MemoryDataWidth | Init->BurstAccessMode | Init->WaitSignalPolarity | Init->WrapMode | Init->WaitSignalActive |\
Init->WriteOperation | Init->WaitSignal | Init->ExtendedMode | Init->AsynchronousWait | Init->WriteBurst ) \
);
}
else
{
MODIFY_REG(Device->BTCR[Init->NSBank], \
(FSMC_BCRx_FACCEN | FSMC_BCRx_MUXEN | FSMC_BCRx_MTYP | \
FSMC_BCRx_MWID | FSMC_BCRx_BURSTEN | FSMC_BCRx_WAITPOL | FSMC_BCRx_WRAPMOD | FSMC_BCRx_WAITCFG | \
FSMC_BCRx_WREN | FSMC_BCRx_WAITEN | FSMC_BCRx_EXTMOD | FSMC_BCRx_ASYNCWAIT | FSMC_BCRx_CBURSTRW), \
(FSMC_NORSRAM_FLASH_ACCESS_DISABLE | Init->DataAddressMux | Init->MemoryType | \
Init->MemoryDataWidth | Init->BurstAccessMode | Init->WaitSignalPolarity | Init->WrapMode | Init->WaitSignalActive |\
Init->WriteOperation | Init->WaitSignal | Init->ExtendedMode | Init->AsynchronousWait | Init->WriteBurst ) \
);
}
return HAL_OK;
}
/**
* @brief Initialize the FSMC_NORSRAM device according to the specified
* control parameters in the FSMC_NORSRAM_InitTypeDef
* @param Device: Pointer to NORSRAM device instance
* @param Init: Pointer to NORSRAM Initialization structure
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef* Init)
{
uint32_t tmpr = 0;
/* Check the parameters */
assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
assert_param(IS_FSMC_MUX(Init->DataAddressMux));
assert_param(IS_FSMC_MEMORY(Init->MemoryType));
assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
/* Set NORSRAM device control parameters */
tmpr = (uint32_t)(Init->DataAddressMux |\
Init->MemoryType |\
Init->MemoryDataWidth |\
Init->BurstAccessMode |\
Init->WaitSignalPolarity |\
Init->WrapMode |\
Init->WaitSignalActive |\
Init->WriteOperation |\
Init->WaitSignal |\
Init->ExtendedMode |\
Init->AsynchronousWait |\
Init->WriteBurst
);
if(Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
{
tmpr |= (uint32_t)FSMC_NORSRAM_FLASH_ACCESS_ENABLE;
}
Device->BTCR[Init->NSBank] = tmpr;
return HAL_OK;
}
/**
* @brief Initializes the FSMC NOR/SRAM Banks according to the specified
* parameters in the FSMC_NORSRAMInitStruct.
* @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef
* structure that contains the configuration information for
* the FSMC NOR/SRAM specified Banks.
* @retval None
*/
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
{
/* Check the parameters */
assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));
/* Bank1 NOR/SRAM control register configuration */
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
FSMC_NORSRAMInitStruct->FSMC_MemoryType |
FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
FSMC_NORSRAMInitStruct->FSMC_WrapMode |
FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
{
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)FSMC_BCR1_FACCEN;
}
/* Bank1 NOR/SRAM timing register configuration */
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
/* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
{
assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
}
else
{
FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
}
}