IX_STATUS ixParityENAccAqmPEDetectionConfigure (IxParityENAccAqmPEConfigOption ixAqmPDCfg) { UINT32 aqmPDCfgFlags = IXP400_PARITYENACC_AQM_QUEADDRERR_PERR_ENABLE; UINT32 aqmPDCfgStatus = 0; UINT32 aqmTmpPDCfgStatus = 0; /* Enable parity error detection */ if (IXP400_PARITYENACC_PE_ENABLE == ixAqmPDCfg) { IXP400_PARITYENACC_VAL_BIT_SET(aqmPDCfgStatus, aqmPDCfgFlags); } else /* Disable parity error detection */ { IXP400_PARITYENACC_VAL_BIT_CLEAR(aqmPDCfgStatus, aqmPDCfgFlags); } /* end of if */ /* * The following sequence of steps works without the following while loop on Emulator * but doesn't work on BMP */ while (TRUE != IXP400_PARITYENACC_VAL_BIT_CHECK(aqmTmpPDCfgStatus, aqmPDCfgStatus)) { /* Set the new configuration */ IXP400_PARITYENACC_REG_WRITE ( ixParityENAccAqmPEConfig.aqmPERegisters.aqmQueAddErr, aqmPDCfgStatus); /* Verify that the configuration is successful or not */ IXP400_PARITYENACC_REG_READ( ixParityENAccAqmPEConfig.aqmPERegisters.aqmQueAddErr,&aqmTmpPDCfgStatus); } if (TRUE == IXP400_PARITYENACC_VAL_BIT_CHECK(aqmTmpPDCfgStatus, aqmPDCfgStatus)) { return (IXP400_PARITYENACC_PE_ENABLE == ixAqmPDCfg) ? ixParityENAccIcInterruptEnable( IXP400_PARITYENACC_INTC_AQM_PARITY_INTERRUPT) : ixParityENAccIcInterruptDisable( IXP400_PARITYENACC_INTC_AQM_PARITY_INTERRUPT); } else { return IX_FAIL; } /* end of if */ } /* end of ixParityENAccAqmPEDetectionConfigure() function */
IX_STATUS ixParityENAccEbcPEParityErrorContextFetch( IxParityENAccEbcPEParityErrorContext *ixEbcPECMsg) { if ((IxParityENAccEbcPEParityErrorContext *)NULL == ixEbcPECMsg) { return IX_FAIL; } /* end of if */ /* Fetch EBC Parity Error Status */ ixParityENAccEbcPEParityErrorStatusGet(); ixEbcPECMsg->ebcParityAddress = IXP400_PARITYENACC_VAL_READ( ixParityENAccEbcPEConfig.ebcParityErrorStatus.expParityStatusValue, IXP400_PARITYENACC_EBC_PARITY_STATUS_ERRADDR); /* Detected Parity Error on Inbound Write by an External Master? */ if (IXP400_PARITYENACC_VAL_BIT_CHECK( ixParityENAccEbcPEConfig.ebcParityErrorStatus.expParityStatusValue, IXP400_PARITYENACC_EBC_PARITY_STATUS_INERRSTS)) { ixEbcPECMsg->ebcParitySource = IXP400_PARITYENACC_PE_EBC_EXTMST; ixEbcPECMsg->ebcAccessType = IXP400_PARITYENACC_PE_WRITE; return IX_SUCCESS; } /* end of if */ /* Detected Parity Error on Outbound Read by the Expansion Bus Controller? */ if (IXP400_PARITYENACC_VAL_BIT_CHECK( ixParityENAccEbcPEConfig.ebcParityErrorStatus.expParityStatusValue, IXP400_PARITYENACC_EBC_PARITY_STATUS_OUTERRSTS)) { ixEbcPECMsg->ebcParitySource = IXP400_PARITYENACC_PE_EBC_CS; ixEbcPECMsg->ebcAccessType = IXP400_PARITYENACC_PE_READ; return IX_SUCCESS; } /* end of if */ #ifndef NDEBUG IXP400_PARITYENACC_MSGLOG(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, "ixParityENAccEbcPEParityErrorContextFetch(): " "Can't fetch parity context of EBC #%u!!!\n", 0,0,0,0,0,0); #endif /* end of #ifndef NDEBUG */ return IX_FAIL; } /* end of ixParityENAccEbcPEParityErrorContextFetch() function */
IX_STATUS ixParityENAccPbcPEParityErrorContextFetch( IxParityENAccPbcPEParityErrorContext *ixPbcPECMsg) { BOOL isrPPE = FALSE; BOOL srcrDPE = FALSE; BOOL srcrMDPE = FALSE; if ((IxParityENAccPbcPEParityErrorContext *)NULL == ixPbcPECMsg) { return IX_FAIL; } /* end of if */ /* Fetch PBC Parity Error Status into local data structures*/ ixParityENAccPbcPEParityErrorStatusGet(); /* * PCI Controller Initiator/Target Interface and Parity Errors detection * during Read / Write Transactions show in the following decision table * * +--------------------+--------------------+ * | PCI Initiator | PCI Target | * +----------+---------+----------+---------+ * | Read | Write | Read | Write | * +----------+---------+----------+---------+ * isr.PPE | 1 | 1 | - | 1 | * +----------+---------+----------+---------+ * srcr.DPE | 1 | 0 | - | 1 | * +----------+---------+----------+---------+ * srcr.MDPE | 1 | 1 | - | 0 | * +----------+---------+----------+---------+ * * While: * - Error handling is left to initiator of transaction * 1 Bit in the register (row heading-reg.BIT) is SET * 0 Bit in the register is CLEAR * x Don't Care */ isrPPE = IXP400_PARITYENACC_VAL_BIT_CHECK( ixParityENAccPbcPEConfig.pbcParityErrorStatus.pciIsrValue, (UINT32) IXP400_PARITYENACC_PBC_ISR_PPE); srcrDPE = IXP400_PARITYENACC_VAL_BIT_CHECK( ixParityENAccPbcPEConfig.pbcParityErrorStatus.pciSrcrValue, (UINT32) IXP400_PARITYENACC_PBC_PCICFG_SRCR_DPE); srcrMDPE = IXP400_PARITYENACC_VAL_BIT_CHECK( ixParityENAccPbcPEConfig.pbcParityErrorStatus.pciSrcrValue, (UINT32) IXP400_PARITYENACC_PBC_PCICFG_SRCR_MDPE); /* Is Parity Error Detected ? */ if (TRUE == isrPPE) { /* Is due to PCI Initiator Transaction ? */ if (TRUE == srcrMDPE) { /* Is due to PCI Initiator Read Transaction ? */ if (TRUE == srcrDPE) { ixPbcPECMsg->pbcParitySource = IXP400_PARITYENACC_PE_PBC_INITIATOR; ixPbcPECMsg->pbcAccessType = IXP400_PARITYENACC_PE_READ; return IX_SUCCESS; } /* else of if */ /* Is due to PCI Initiator Write Transaction ? */ else { ixPbcPECMsg->pbcParitySource = IXP400_PARITYENACC_PE_PBC_INITIATOR; ixPbcPECMsg->pbcAccessType = IXP400_PARITYENACC_PE_WRITE; return IX_SUCCESS; } /* end of if */ } /* end of if */ /* Is due to PCI Target Write Transaction ? */ if (TRUE == srcrDPE) { ixPbcPECMsg->pbcParitySource = IXP400_PARITYENACC_PE_PBC_TARGET; ixPbcPECMsg->pbcAccessType = IXP400_PARITYENACC_PE_WRITE; return IX_SUCCESS; } /* end of if */ /* Is due to PCI Target Read Transaction? Possibly */ ixPbcPECMsg->pbcParitySource = IXP400_PARITYENACC_PE_PBC_TARGET; ixPbcPECMsg->pbcAccessType = IXP400_PARITYENACC_PE_READ; return IX_SUCCESS; } /* end of if */ #ifndef NDEBUG IXP400_PARITYENACC_MSGLOG(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, "ixParityENAccPbcPEParityErrorContextFetch(): " "Can't fetch parity context of PBC !!!\n", 0,0,0,0,0,0); #endif /* end of #ifndef NDEBUG */ return IX_FAIL; } /* end of function */
IX_STATUS ixParityENAccPbcPEDetectionConfigure(IxParityENAccPbcPEConfigOption ixPbcPDCfg) { UINT32 pbcPDCfgStatus = 0; UINT32 pbcTmpPDCfgStatus = 0; int loopIdx = 0; /* Read the PCI Controller PCI Config SRCR register */ IXP400_PARITYENACC_REG_WRITE( ixParityENAccPbcPEConfig.pbcPERegisters.pciCrpAdCbe, IXP400_PARITYENACC_PBC_PCICSR_SRCR_READ); IXP400_PARITYENACC_REG_READ( ixParityENAccPbcPEConfig.pbcPERegisters.pciCrpRdata, &pbcPDCfgStatus); /* * Set/Clear the PER bit of SRCR register & * Enable/Disable Parity Error Notification */ if (IXP400_PARITYENACC_PE_ENABLE == ixPbcPDCfg) { /* Set the PER bit of SRCR register */ IXP400_PARITYENACC_VAL_BIT_SET(pbcPDCfgStatus, IXP400_PARITYENACC_PBC_PCICFG_SRCR_PER); /* Enable the PCI Parity Error Interrupt Notification */ IXP400_PARITYENACC_REG_BIT_SET( ixParityENAccPbcPEConfig.pbcPERegisters.pciInten, IXP400_PARITYENACC_PBC_INTEN_PPE); } /* else of if */ else { /* Clear the PER bit of SRCR register */ IXP400_PARITYENACC_VAL_BIT_CLEAR(pbcPDCfgStatus, IXP400_PARITYENACC_PBC_PCICFG_SRCR_PER); /* Disable the PCI Parity Error Interrupt Notification */ IXP400_PARITYENACC_REG_BIT_CLEAR( ixParityENAccPbcPEConfig.pbcPERegisters.pciInten, IXP400_PARITYENACC_PBC_INTEN_PPE); } /* end of if */ /* Write back the PCI Controller PCI Config SRCR register */ IXP400_PARITYENACC_REG_WRITE( ixParityENAccPbcPEConfig.pbcPERegisters.pciCrpAdCbe, IXP400_PARITYENACC_PBC_PCICSR_SRCR_WRITE); IXP400_PARITYENACC_REG_WRITE( ixParityENAccPbcPEConfig.pbcPERegisters.pciCrpWdata, pbcPDCfgStatus); loopIdx = 10; while (loopIdx--) { /* Verify that the configuration is successful or not */ IXP400_PARITYENACC_REG_WRITE( ixParityENAccPbcPEConfig.pbcPERegisters.pciCrpAdCbe, IXP400_PARITYENACC_PBC_PCICSR_SRCR_READ); IXP400_PARITYENACC_REG_READ( ixParityENAccPbcPEConfig.pbcPERegisters.pciCrpRdata, &pbcTmpPDCfgStatus); } if (TRUE == IXP400_PARITYENACC_VAL_BIT_CHECK(pbcPDCfgStatus, pbcTmpPDCfgStatus)) { /* Enable/Disable the corresponding interrupt at Interrupt Controller */ return (IXP400_PARITYENACC_PE_ENABLE == ixPbcPDCfg) ? ixParityENAccIcInterruptEnable( IXP400_PARITYENACC_INTC_PBC_PARITY_INTERRUPT) : ixParityENAccIcInterruptDisable( IXP400_PARITYENACC_INTC_PBC_PARITY_INTERRUPT); } else { return IX_FAIL; } /* end of if */ } /* end of ixParityENAccPbcPEDetectionConfigure() function */