void
ixParityENAccMcuPEParityErrorStatusTransform (
IxParityENAccMcuPEParityErrorContext *ixMcuPECMsg,
UINT32 mcuElogNValue,
UINT32 mcuEcarNValue)
{
/*
* Input parameter validation is not done in the local functions
* to avoid extra code.
*/
/* ECC/parity error is of Single or Multi bit type */
ixMcuPECMsg->mcuParitySource =
(IXP400_PARITYENACC_MCU_ERR_SMBIT_SGL ==
IXP400_PARITYENACC_VAL_READ(mcuElogNValue,
IXP400_PARITYENACC_MCU_ERR_SMBIT_MASK)) ?
IXP400_PARITYENACC_PE_MCU_SBIT : IXP400_PARITYENACC_PE_MCU_MBIT;
/* Identify Read or Write access that has caused parity error */
ixMcuPECMsg->mcuAccessType =
(IXP400_PARITYENACC_MCU_ERR_RW_READ ==
IXP400_PARITYENACC_VAL_READ(mcuElogNValue,
IXP400_PARITYENACC_MCU_ERR_RW_MASK)) ?
IXP400_PARITYENACC_PE_READ : IXP400_PARITYENACC_PE_WRITE;
/* Fetch the parity error syndrome */
ixMcuPECMsg->mcuParityData = (IxParityENAccPEParityErrorData)
IXP400_PARITYENACC_VAL_READ(mcuElogNValue,
IXP400_PARITYENACC_MCU_ERR_SYNDROME_MASK);
/* Identify the requesting interface to the MCU */
ixMcuPECMsg->mcuRequester =
(IXP400_PARITYENACC_MCU_ERR_MASTER_CORE_BIU ==
IXP400_PARITYENACC_VAL_READ(mcuElogNValue,
IXP400_PARITYENACC_MCU_ERR_MASTER_MASK)) ?
IXP400_PARITYENACC_PE_MCU_MPI : IXP400_PARITYENACC_PE_MCU_AHB_BUS;
/* Feth the parity error address */
ixMcuPECMsg->mcuParityAddress = (IxParityENAccPEParityErrorAddress)
IXP400_PARITYENACC_VAL_READ(mcuEcarNValue,
IXP400_PARITYENACC_MCU_ERR_ADDRESS_MASK);
} /* end of ixParityENAccMcuPEParityErrorStatusTransform() function */
IX_STATUS
ixParityENAccEbcPEParityErrorContextFetch(
IxParityENAccEbcPEParityErrorContext *ixEbcPECMsg)
{
if ((IxParityENAccEbcPEParityErrorContext *)NULL == ixEbcPECMsg)
{
return IX_FAIL;
} /* end of if */
/* Fetch EBC Parity Error Status */
ixParityENAccEbcPEParityErrorStatusGet();
ixEbcPECMsg->ebcParityAddress = IXP400_PARITYENACC_VAL_READ(
ixParityENAccEbcPEConfig.ebcParityErrorStatus.expParityStatusValue,
IXP400_PARITYENACC_EBC_PARITY_STATUS_ERRADDR);
/* Detected Parity Error on Inbound Write by an External Master? */
if (IXP400_PARITYENACC_VAL_BIT_CHECK(
ixParityENAccEbcPEConfig.ebcParityErrorStatus.expParityStatusValue,
IXP400_PARITYENACC_EBC_PARITY_STATUS_INERRSTS))
{
ixEbcPECMsg->ebcParitySource = IXP400_PARITYENACC_PE_EBC_EXTMST;
ixEbcPECMsg->ebcAccessType = IXP400_PARITYENACC_PE_WRITE;
return IX_SUCCESS;
} /* end of if */
/* Detected Parity Error on Outbound Read by the Expansion Bus Controller? */
if (IXP400_PARITYENACC_VAL_BIT_CHECK(
ixParityENAccEbcPEConfig.ebcParityErrorStatus.expParityStatusValue,
IXP400_PARITYENACC_EBC_PARITY_STATUS_OUTERRSTS))
{
ixEbcPECMsg->ebcParitySource = IXP400_PARITYENACC_PE_EBC_CS;
ixEbcPECMsg->ebcAccessType = IXP400_PARITYENACC_PE_READ;
return IX_SUCCESS;
} /* end of if */
#ifndef NDEBUG
IXP400_PARITYENACC_MSGLOG(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR,
"ixParityENAccEbcPEParityErrorContextFetch(): "
"Can't fetch parity context of EBC #%u!!!\n", 0,0,0,0,0,0);
#endif /* end of #ifndef NDEBUG */
return IX_FAIL;
} /* end of ixParityENAccEbcPEParityErrorContextFetch() function */
IX_STATUS
ixParityENAccAqmPEParityErrorContextFetch
(IxParityENAccAqmPEParityErrorContext *ixAqmPECMsg)
{
/* Validate parameters */
if ((IxParityENAccAqmPEParityErrorContext *)NULL == ixAqmPECMsg)
{
return IX_FAIL;
} /* end of if */
/* For AQM it is always the read access to the SRAM */
ixAqmPECMsg->aqmAccessType = IXP400_PARITYENACC_PE_READ;
/* AQM as parity error source */
ixAqmPECMsg->aqmParitySource = IXP400_PARITYENACC_PE_AQM;
/*
* Read the raw parity error status into local data structure
* from the Address/Control and Data registers of the AQM
*/
IXP400_PARITYENACC_REG_READ(
ixParityENAccAqmPEConfig.aqmPERegisters.aqmQueAddErr,
&ixParityENAccAqmPEConfig.aqmParityErrorStatus.aqmQueAddErrValue);
IXP400_PARITYENACC_REG_READ(
ixParityENAccAqmPEConfig.aqmPERegisters.aqmQueDataErr,
&ixParityENAccAqmPEConfig.aqmParityErrorStatus.aqmQueDataErrValue);
/* Parity error address and data */
ixAqmPECMsg->aqmParityAddress =
IXP400_PARITYENACC_VAL_READ(
ixParityENAccAqmPEConfig.aqmParityErrorStatus.aqmQueAddErrValue,
IXP400_PARITYENACC_AQM_QUEADDRERR_PERR_ADDRESS);
ixAqmPECMsg->aqmParityData =
ixParityENAccAqmPEConfig.aqmParityErrorStatus.aqmQueDataErrValue;
return IX_SUCCESS;
} /* end of ixParityENAccAqmPEParityErrorContextFetch() function */
IX_STATUS
ixParityENAccMcuPEParityInterruptClear (
IxParityENAccMcuPEParityErrorSource ixMcuParityErrSrc,
IxParityENAccPEParityErrorAddress ixMcuParityErrAddress)
{
BOOL mcuParityError0 = FALSE;
BOOL mcuParityError1 = FALSE;
BOOL mcuParityErrorN = FALSE;
UINT32 mcuParitySource0 = IXP400_PARITYENACC_MCU_ERR_SMBIT_SGL;
UINT32 mcuParitySource1 = IXP400_PARITYENACC_MCU_ERR_SMBIT_SGL;
register IxParityENAccMcuPERegisters *mcuPERegisters =
&ixParityENAccMcuPEConfig.mcuPERegisters;
IxParityENAccPEParityErrorAddress mcuParityErrorAddr =
IXP400_PARITYENACC_VAL_READ(ixParityENAccMcuPEConfig.\
mcuParityErrorStatus.mcuEcar0Value, IXP400_PARITYENACC_MCU_ERR_ADDRESS_MASK);
/* Identify the Multi & Single bit parity errors */
ixParityENAccMcuPEParityErrorStatusInterpret (
&mcuParityError0, &mcuParityError1, &mcuParityErrorN,
&mcuParitySource0, &mcuParitySource1);
switch (ixMcuParityErrSrc)
{
case IXP400_PARITYENACC_PE_MCU_SBIT:
{
/* Parity error number #0 is of single bit type */
if ((TRUE == mcuParityError0) &&
(IXP400_PARITYENACC_MCU_ERR_SMBIT_SGL == mcuParitySource0) &&
(mcuParityErrorAddr == ixMcuParityErrAddress))
{
/* Write '1' to clear the single bit parity interrupt */
IXP400_PARITYENACC_REG_WRITE(mcuPERegisters->mcuMcisr,
IXP400_PARITYENACC_MCU_ERROR0_MASK);
break;
} /* end of if */
/* Parity error number #1 is of single bit type */
/* Write '1' to clear the single bit parity interrupt */
IXP400_PARITYENACC_REG_WRITE(mcuPERegisters->mcuMcisr,
IXP400_PARITYENACC_MCU_ERROR1_MASK);
break;
} /* end of case IXP400_PARITYENACC_PE_MCU_SBIT */
case IXP400_PARITYENACC_PE_MCU_MBIT:
{
/* Parity error number #0 is of multi bit type */
if ((TRUE == mcuParityError0) &&
(IXP400_PARITYENACC_MCU_ERR_SMBIT_MLT == mcuParitySource0) &&
(mcuParityErrorAddr == ixMcuParityErrAddress))
{
/* Write '1' to clear the multi bit parity interrupt */
IXP400_PARITYENACC_REG_WRITE(mcuPERegisters->mcuMcisr,
IXP400_PARITYENACC_MCU_ERROR0_MASK);
break;
} /* end of if */
/* Parity error number #1 is of multi bit type */
/* Write '1' to clear the multi bit parity interrupt */
IXP400_PARITYENACC_REG_WRITE(mcuPERegisters->mcuMcisr,
IXP400_PARITYENACC_MCU_ERROR1_MASK);
break;
} /* end of case IXP400_PARITYENACC_PE_MCU_MBIT */
case IXP400_PARITYENACC_PE_MCU_OVERFLOW:
{
/* Write '1' to clear the Parity Overflow Interrupt */
IXP400_PARITYENACC_REG_WRITE(mcuPERegisters->mcuMcisr,
IXP400_PARITYENACC_MCU_ERRORN_MASK);
break;
} /* end of case IXP400_PARITYENACC_PE_MCU_OVERFLOW */
default:
{
/* This part of the code should never be reached */
IXP400_PARITYENACC_MSGLOG(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR,
"ixParityENAccMcuPEParityInterruptClear(): "
"Invalid MCU interrupt source to clear\n", 0,0,0,0,0,0);
return IX_FAIL;
} /* end of case default */
} /* end of switch */
return IX_SUCCESS;
} /* end of ixParityENAccMcuPEParityInterruptClear() function */
